Contributed by Dick James
Two weeks ago, we posted about the TSMC 20 nm product that we had in-house; now after waiting for a year since Samsung’s announcement of V-NAND production, we have that in the lab and can start to see what it looks like.
The vertical flash was first released in an enterprise solid-state drive (SSD) last year, in 960 GB and 480 GB versions, but with no model number, so essentially for sampling only to established customers. Then in May this year, they announced a second-generation V-NAND SSD, with a stack of 32 cell layers.
However, on July 1 at this year’s Samsung SSD Global Summit they unveiled the SSD 850 Pro, aimed at high-end PCs and workstations, and said to be available in July. Of course we immediately put out feelers and got some on pre-order. They showed up last week and we have the first few images.
First, though, let’s think about what the changes are from the conventional planar NAND. Samsung posted a slick video which gives a summary of the technology. The first thing to note is that we have gone from the ETOX floating-gate charge storage that we have seen in the last umpteen generations of flash, to charge-trap storage (CTF – Charge Trap Flash) in which the charge is stored on a silicon nitride layer (otherwise known as a SONOS cell – Si/SiO/SiN/SiO/Si).
The SONOS stack is then oriented vertically, using a polysilicon cylinder as the substrate silicon, and wrapping the other layers around the central cylinder.
Fig. 1 Cell structure transition from planar to V-NAND stack
The wordlines (control gates) become a horizontal layer, and the bitlines are connected to the top of the polySi cylinder; the select gates are formed by the top and bottom conductive layers . Samsung describes the use of a tungsten replacement metal gate , and 24 wordline layers plus 2 dummy wordlines and two select gates for a total of 28 layers .
Fig. 2 Schematic of V-NAND cell stack
We also see in Fig.2 a “blocking layer” in between the metal gate and the SiN, which at least implies the use of a high-k dielectric instead of an oxide layer for the capacitative coupling layer, as used in their CTF parts from 2006.
One of the many challenges using a vertical stack such as the V-NAND is etching through a stack of many dissimilar layers, to etch the holes for the polySi cylinder channels, the slots through the stack to separate the wordlines, and the vias down to the wordlines (etching holes down to a staircase of extended wordlines). In fact, the whole stack is a big etching problem – see Fig.3.
Fig. 3 Schematic of etching steps in V-NAND stack
Now that we have the production part, Samsung have clearly solved those problems. Let’s take a first look at what’s inside. The image below is a photo of the die, and the following image shows the die mark – the “A” on the end denoting the second-generation product. Interestingly, the “DG” in the part number normally denotes a 128-Gb die, but this part is actually ~86 Gb, since we have twelve flash dies in our 128-GB solid-state drive.
The part described in the ISSCC paper  was an actual 128-Gb device, with a chip size of ~133 sq. mm. Our 86-Gb die has shrunk to ~85 sq.mm., slightly increasing the bit density from 0.96 to 0.99 Gb/sq.mm.
When we cross-section the chip, the staircase below shows up nicely:
In this first shot, we don’t appear to have sectioned through any of the vias to the wordline layers; the vertical features appear to be polySi cylinders drilled into the outer edges of the stack. If we look closer at the edge of the array, that does appear to be the case.
On the left side of the image we can see the array proper. SEM images can always be confusing, but it appears that the polySi bitline cylinders are staggered, and the slots between wordlines are filled with tungsten to contact the substrate for the lower select transistors. The image below shows things in a little more detail, and we can clearly see that the bitline contacts are staggered. We can also see that there are 38 layers in the stack; 32 wordlines, plus four dummy wordlines, plus the select transistors at top and bottom.
At the moment, that’s as far as we’ve got; we don’t yet have any materials analysis, but my guess is that the three interconnect layers are tungsten, copper and aluminum, as in a lot of other Samsung memory chips.
By coincidence, this week the Flash Memory Summit is going on, and at a keynote there Bob Brennan announced a 3-bit/cell version of the V-NAND flash that will be shipped in a few weeks. Rick Merritt of EETimes was there and gave us a summary.
In order to continue to provide you with the most reliable and insightful competitive intelligence in the industry, Chipworks will be preparing two reports on this seminal part.
- Package analysis report
- Structural analysis report
Our experienced engineers and analysts deliver top-notch investigative results. You can expect a comprehensive, factual, and detailed report which will give you a solid understanding of your product and market position, and more importantly – your potential. For more details contact Chipworks, or keep an eye on Twitter @ChipworksDick. Once the dust has settled, I hope to get into a bit more detail in a future blog in a few months time.
 J. Jang et al., “Vertical Cell Array using TCAT (Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory“, Dig. Symp. VLSI Tech., pp. 192-193, June 2009
 K-T Park et al., “Three-Dimensional 128Gb MLC Vertical NAND Flash-Memory with 24-WL Stacked Layers and 50MB/sHigh-Speed Programming“, Proc. ISSCC, pp. 334-335, Feb. 2014