First Volume Production Phase Change Memory by Micron

Posted on May 23, 2013 by Chipworks

A Peak Inside the Micron 1 Gb, 45 nm PCM

By: Rajesh Krishnamurthy

Phase change memory (PCM) combines the nonvolatile attributes of flash memories like NOR and NAND types, combined with the bit alterability and fast reads and writes of RAM or EEPROM. This positions PCM to potentially provide memory solutions in the memory subsystems of cellular phones, PCs, and embedded and consumer electronics applications. Micron (previously Numonyx) and Samsung have already previously demonstrated a NOR compatible PCM for commercial applications. However, Micron has previously never managed to manufacture dense PCM memory for mobile applications, even though in an IEDM 2009⁽¹⁾ paper, they demonstrated a 1 Gb PCM memory array with 0.015 µm² cell size (5.5F²) using 45 nm generation PCM technology. In 2011, Samsung, the other significant player in bringing PCM technology to commercial products, managed to bring a NOR-compatible 65 nm PCM memory to market and used it in Samsung GT-E2550 GSM feature phones (analyzed previously by Chipworks⁽²⁾), though it was used in a limited number of phones. In early 2013, Micron has mass produced their next generation PCM intended for mobile phone applications, a 45 nm PCM which is a shrink from their previous 90 nm PCM. Unlike their previous generation PCM products and unlike Samsung’s NOR compatible PCM multichip package (MCP) consisting of PCM and UTRAM dies, this 45 nm Micron PCM is packaged in an MCP, uses an LPDDR2 interface, and shares the same memory bus between the LPDDR2-PCM and LPDDR2-SDRAM dies in the MCP.

Chipworks found Micron’s 1 Gb PCM chips in a low-end smartphone from Nokia, shown in Figure 1.

Figure 1 Nokia Smartphone

Figure 2 is a top-view photograph of the Micron PCM MCP on the main printed circuit board of the Nokia smartphone.

Figure 2 Micron PCM MCP on Nokia Phone Main PCB

Figure 3 shows the top and bottom photographs of the MT66R7072A PCM-based MCP extracted from the Nokia smartphone.

Figure 3 Micron LPDDR2 PCM – LPDDR2 SDRAM MCP

The PCM MCP is a 121 ball FBGA package with package dimensions 11 mm x 10 mm x 0.9 mm (thick). A side-view X-ray image of the MT66R7072A PCM, shown in Figure 4, reveals that the PCM MCP is a 1 Gb LPDDR2-PCM die co-packaged with a 512 Mb LPDDR2 die.

Figure 4 Side-View X-Ray Image of the PCM and LPDDR2 SDRAM MCP

Figure 5 shows the die photograph of the MT66R7072A PCM.

Figure 5 Micron 45 nm PCM Die Photograph

The PCM die is manufactured using three levels of Cu metal plus a top level of Al metal in a 45 nm BiCMOS process. Figure 6 shows an overview and detailed SEM cross section of the PCM, while Figure 7 shows SEM plan-view images of the PCM cell delayered to metal 1 running just above the phase change layer, contacts, and substrate diffusion. The Micron PCM has a cell area of 0.011 µm² which is about 58% smaller compared to the 0.026 µm² cell area for the Samsung 512 Mb PCM cell manufactured in a 65 nm BiCMOS process, or 90% smaller compared to the 0.10 µm² cell area for the Numonyx 128 Mb PCM cell manufactured in a 90 nm BiCMOS process; both parts previously analyzed by Chipworks. This cell size reduction is more aggressive than what would be expected from just a process node shrink from 90 nm to 45 nm. The aggressive shrink in cell size is facilitated by adopting a vertical access device and arranging the memory cell in a 5.5F² design. The 5.5F² memory cell design includes wordline (access device base) contacts shared by four PCM lines. A PCM cell is placed at the intersection of PCM lines and wordlines. A thick STI separates wordlines while a thin STI separates the adjacent emitters and the base contacts. The effective cell size of the 5.5F² memory cell will be slightly larger than the equivalent 4F² cross-point cell adopted by Samsung for their 65 nm PCM device. Micron claims in an IEDM 2009 paper⁽¹⁾ that the marginal disadvantage in the increased effective cell size is trumped by the significant reduction in the voltage drop on the wordline (base access) resistance.

Figure 6 Overview and Detailed SEM Cross Sections of Micron 45 nm PCM

Figure 6 (L) Overview and Detailed SEM Cross Sections of Micron 45 nm PCM. Figure 7 (R) SEM Plan Views of Micron 45 nm PCM at Metal 1 Bitlines Parallel to PCM Lines, Contacts, and Diffusion

Micron has taken a leading position in the scalable PCM technology with this MT66R7072A, produced in volume to be used in commercial smartphones. Volume production of high density PCM memory is a significant milestone, due to its simpler structure and significant cell size reduction. Samsung, the only other serious player with commercial PCM products, has demonstrated in a 2010 publication⁽³⁾ further scaling of the PCM cell down to sub-20 nm technology (F=17 nm), by using the same overall approach of stacking PCM lines directly over the access device.

1. G.Servalli, “A 45 nm Generation Phase Change Memory Technology,” IEDM 2009, pg 113
2. http://www.chipworks.com/blog/technologyblog/2011/05/24/a-peek-inside-the-samsung-512-mb-4f2-cross-point-phase-change-memory/
3. I.S Kim et. al, “High Performance PRAM Cell Scalable to sub-20 nm Technology with below 4F² Cell Size, Extendable to DRAM Applications,” 2009 VLSI Technology Digest of Technical Papers, 2009, pg 203

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ISPSD 2013

Posted on May 22, 2013 by Chipworks

Contributed by: St.J. Dixon-Warren

The 25^th annual International Symposium on Power Semiconductor Devices will be held in the historic seaside city of Kanazawa, Ishikawa Prefecture, Japan. Chipworks will be participating as an exhibitor, plus we plan to participate in the technical sessions, since it is great place for us to monitor new developments in power electronics, especially at the device level. Below is some of the artwork that will be featured in our booth (click to enlarge).

As in previous years, the Short Course program will be offered on the Sunday before the main conference begins. The topics look interesting, and including

“High Voltage Bipolar Devices: the past, present and future” by Dieter Silber (University of Bremen)
“The superjunction concept from high-voltage to low-voltage and from vertical to lateral power devices” by Florin Udrea (Cambridge University)
“Integrated Power Converters – Basic Concepts” by Wai Tung Ng (University of Toronto)
“Fundamentals and Frontiers of SiC Power Device Technology” by Tsunenobu Kimoto (Kyoto University)
“IGBT-Modules – Packaging and reliability” by Josef Lutz (Chemnitz University)

The conference opens on the Monday morning with two plenary sessions, chaired by G. Majumdar of Mitsubishi and K. Hamada of Toyota. The first plenary, by M. Yamamoto of Mitsubishi, concerns the Development of secured energy infrastructure in Japan, which will be a timely topic given the troubles in Japan’s nuclear power industry caused by the earthquake and tsunami in March 2011. Apparently, prior to the March 2011 Japan generated about 30% of their power from nuclear energy. As of September 2012 only two of Japan’s fifty reactors were still operating (source: The Economist). The second plenary, by S. Linder of ABB, is on the topic of Power Electronics: The Key Enabler of a Future with more than 20% Wind and Solar Electricity. Wind and solar power are intermittent sources of energy. Managing and maintaining stability in the electrical power grid while using intermittent power sources is a challenging technical problem, which requires the clever use of power electronics devices. ABB manufactures large wafer-scale thyristors and other devices that are critical to operation of the grid. The third plenary, presented by D. Tan of the IEEE Power Electronics Society, is on the topic of High Efficiency DC Power Delivery.

The Conferences continues from Monday to Thursday with sessions on the following topics:

High Voltage Power Devices (mainly IGBTs)
New Material Power Devices (more specifically GaN and SiC transistors)
Power ICs (mostly Smart Power BCD technology but also gate driver ICs)
Low Voltage Power Devices (largely low voltage MOSFET technology)
Module and Package Technologies

The conference also features a poster session and several social events, including a banquet. The conference closes with presentation of the awards.

As mentioned, Chipworks is participating as an exhibitor again this year. Attendees are invited to drop by our booth to pick up a Chipworks puzzle to solve. We’ll have recent reports and analyses available to review. We plan to publish a follow on blog posting with highlights of the conference. Stay tuned!

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Infineon 130 nm Smart Power BCD Technology

Posted on May 8, 2013 by Chipworks

Contributed by: Sinjin Dixon-Warren and Paul Jagodzinski

The approach of ISPSD 2013, which will be held this year in Kanazawa, Japan, May 26-30, stimulated us to look back at some of our recent analyses of the Infineon 130 nm Smart Power technology and at previous ISPSD proceedings. In particular, at ISPSD 2011, Ralf Rudolf of Infineon presented a paper entitled Automotive 130 nm Smart-Power-Technology including embedded Flash Functionality.

Infineon’s paper described a bulk silicon-based 130 nm bipolar CMOS-DMOS (BCD) technology, which integrated logic, analog, memory, and power switching into one chip. The BCD process offered devices that function in the 1.2 V to 60 V range, and with up to 15 A currents. It featured four layers of copper interconnects, plus one additional top thick copper layer, referred to as power copper. This is one of the first production BCD processes at the 130 nm node, which alone puts it at the leading edge of BCD technology.

Earlier this year, Infineon announced the TLE9832 system-on-chip (SoC) product family produced in the 130 nm BCD technology. It claimed that TLE9832, targeting automotive applications, integrated an 8 bit microcontroller with a LIN transceiver and related peripherals on a single chip. Chipworks has recently completed a full structural analysis of the TLE9832-2QV device and found evidence showing Infineon’s leadership in the BCD technology.

The TLE9832-2QV die photograph shows that the thick power copper layer is used for bond pads, power and ground routing, and as a kind of heat spreader located over the die power transistors. The die markings M9834-B1 © 2010 KALLISTO-V1 indicate a 2010 design.

TLE9832-2QV Die Photograph

The cross-sectional SEM image below shows the TLE9832-2QV general die structure. The die includes four layers of copper interconnects, metal 1 through metal 4, plus a thick metal 5 power Cu layer (which also has additional sub-layers composed of other metals), deep and shallow trench isolation (DTI and STI), and multiple wells. A heavily doped n⁺ buried layer is used in most of the TLE9832-2QV epitaxial wells, defined by the DTI.

TLE9832-2QV General Die Structure

Perhaps the most unusual feature we found in the TLE9832-2QV device is the modification of the deep trench isolation. We believe that this modification may play a role in the suppression of the device’s parasitic transistors, which are inherently associated with the BCD complex well structure and, especially in an advanced BCD technology, can be an area of major concern.

Specifically, the Infineon’s paper points to the lateral NPN1 parasitic transistor which connects two adjacent epitaxial wells, and the vertical NPN2 parasitic transistor which exists between the n⁺ buried layer and an embedded n-well. When an LDMOS stage of a BCD device is used in a bridge driver or in a high side switch, the stage is likely to operate at below ground potential. In such a case, as indicated by the Infineon’s paper, a large electron current may be injected from the underlying n⁺ buried layer into the substrate. Due to the narrow DTI region separating the device’S epitaxial wells, a significant portion of this current will flow into the adjacent epitaxial well as the NPN1 collector current. That of course constitutes a parasitic disturbance coming from the LDMOS area, and therefore is undesirable. As a second effect of the n⁺ buried layer being at a negative potential, the NPN2 transistor may be driven into A low resistance state, and pull the embedded n-well toward ground or even below ground, potentially causing still more disturbance.

Parasitic Bipolar Transistors in the TLE9832-2QV

These parasitic effects seem to be addressed by Infineon through an unusual DTI structure. As you can see in our SEM image, the DTI oxide liner has been removed from the bottom of the trench, and the trench has been filled with polysilicon. We have found that the in-trench polysilicon is heavily doped with phosphorus, and that an n⁺ region exists beneath the trench, obviously due to the phosphorus out-diffusion from the trench into the substrate. This n⁺ region can be considered a collector of a purposely formed NPN3 transistor. The same n⁺ buried layer, which is the emitter of the NPN1, is also the emitter of the NPN3. If the in-trench polysilicon electrode is connected to ground, as annotated in our image, and electrons are injected from the n⁺ buried layer into the substrate, then the electrons get intercepted by the NPN3 collector before they reach the adjacent epitaxial well. In other words, the NPN3 transistor provides a preferential path to ground for the electrons, therefore, preventing any harmful action of the parasitic NPN1. Moreover, due to the lightly doped and narrow base region of the NPN3, if the buried layer voltage drops below ground, the NPN3 transistor might easily reach punchthrough breakdown. That would clamp the buried layer voltage at the breakdown value, limiting the parasitic action of the NPN2 transistor as well.

Actually, we did not expect the innovative NPN3 transistor to be in the TLE9832-2QV. In Infineon’s paper, the in-trench polysilicon appeared to constitute just a p⁺ contact to the p-substrate, without any n-type region beneath the trench. It is likely due to the constant technology development that we often see real life differ from what has been published. Again, it shows the value of reverse engineering, if you really want to know the details of a technology.

As a separate point, we found a whole variety of LDMOS and EDMOS transistors on the TLE9832-2QV chip. Some of them are shown below.

LDMOS and EDMOS Transistors

While the most advanced commercially available smart power BCD processes today are at the 130 nm node, BCD technology continues to be an area of high innovation in the semiconductor industry. The larger geometry BCD technologies continue to be used, like the Texas Instruments LBC5 and LBC7, or Freescale SMARTMOS 8 technologies. New device structures and new process solutions are developed to meet the voltage and current requirements of the real world analog applications, with improved electrical, mechanical, and thermal performance. It seems safe to say that this progress in BCD technology will continue. These technologies are critical in the power conscious world.

Some Related Chipworks Reports

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Intel 22 nm Transistor Measured Using Atomic Force Prober Technology

Posted on May 1, 2013 by Chipworks

Contributed by: St.J. Dixon-Warren

This will be the first in a series of blogs highlighting Chipworks’ advanced node transistor characterization. Chipworks published structural and electrical characterization results for the Intel 22 nm process in May 2012. Measurements of transistor performance on commercially available products must be carried out with nanoprobing. The requirement is to place needle contacts on discrete devices and obtain parametrics without masking or shifting device properties, which means that device probing with FIB circuit edit and a conventional probe station is not feasible – layers are now so thin that it is impossible to eliminate the possibility of FIB induced radiation damage. The data was obtained in partnership with Multiprobe Inc, the leading supplier of Atomic Force Prober (AFP) technology. In this blog, we will review some of these results and compare with published information from Intel. We will also discuss some of the benefits of using AFP technology versus SEM-based probe stations. Our structural analysis of the Intel 22 nm tri-gate finFET technology, which provided the basis for the electrical measurements, has been summarized in my previous blog posting (and also in this blog).

In May 2011, Mark Bohr, Intel Senior Fellow, presented Intel’s 22 nm Transistor Technology. He claimed that the 22 nm finFET geometry provides a steeper sub-threshold slope than planar geometry, which allows the targeting of a lower threshold voltage, as shown in Figure 1.

Figure 1 Intel 22 nm Transfer Characteristics (Source: M. Bohr, Intel)

At the 2012 VLSI Technology conference, C. Auth reported on Intel’s 22 nm SOC technology. They claimed sub-threshold slope (~70 mV/decade) and very low DIBL (~50 mV/V) for the minimum gate length devices, as indicated in Figure 2. He also claimed a ~100 mV reduction in V_T, as compared to the 32 nm process, presented graphically in Figure 3.

Figure 2 Intel 22 nm NMOS and PMOS Transfer Characteristics (Source: C. Auth, Intel)

Figure 3 Intel 22 nm Short Channel Effects (Source: C. Auth, Intel)

Chipworks, in partnership with Multiprobe, has directly measured the L3 cache SRAM transistors found in the 22 nm Intel E3-1230V2 microprocessor. In order to provide the most accurate measurements, Chipworks has exclusively used Multiprobe AFP technology, shown in Figure 4, since 2007 to provide measurements of nanoscale devices.

Figure 4 Multiprobe AFP Technology

The AFP uses atomic force microscopy to resolve the nanoscale features, in particular to identify the transistor contacts, and force feedback control to establish ohmic contact to the device. This approach is used at every major semiconductor manufacturer around the world for critical device measurements. In contrast to the AFM/AFP approach to nanoprobing, scanning electron microscope (SEM) based nanoprobes cause device alteration due to the constant bombardment of electrons. Even when operating the SEM with a minimum acceleration voltage, device V_t shifts, transconductance degrades, I_on reduction and elevation of I_off are unavoidable. Device damage is common to all such tools and has been published repeatedly; a good example for reference was published in 2007, discussing device degradation on 90 nm technology before and after SEM imaging [1]. For Intel’s finFET technology, the concern is even worse as the layout exposes more of the gate area to the bombarding electrons.

The transistor measurements were performed on a die that had been deprocessed to expose the contacts to the six transistors in the SRAM cell. Figure 5 shows that the 0.11 µm² Intel 22 nm SRAM cell layout features butted contacts. The NMOS pull-down transistors (2, 5) contain two transistor fins, while the PMOS pull-up (3, 4) and NMOS access (1, 6) transistors each use a single fin.

Figure 5 Intel 22 nm SRAM Layout (Source: Chipworks)

The transfer characteristics for the NMOS and PMOS transistors of the SRAM cell were measured for V_DS over the range 0.05 V to 1.0 V, see Figure 6 to Figure 8. The data, which is presented on both a log and linear scale, has been normalized to the gate width, which was defined as 2 x fin side length + top semi-circumference, and is 70 nm for the single fin transistors and 140 nm for the double fin transistors.

Figure 6 NMOS Access Transistor Transfer Characteristics (Source: Chipworks/Multiprobe)

Figure 7 NMOS Pull-Down Transfer Characteristics (Source: Chipworks/Multiprobe)

Figure 8 PMOS Pull-Up Transistor Transfer Characteristics (Source: Chipworks/Multiprobe)

The averaged parameters including threshold voltage, DIBL, and sub-threshold slope provided in Table 1, were extracted from the transfer characteristics data. In comparison, using an equivalent AFP prober, Chipworks measured the Intel 32 nm transistors in 2009, and obtained V_TLIN of 0.39 V and -0.44 V for the logic NMOS and PMOS, respectively. The threshold voltage for the 22 nm transistors has decreased by around 100 mV for the NMOS, while the decrease for PMOS is somewhat less. Our measured DIBL is in the same range as that reported by the authors at the 2012 VLSI conference, and the sub-threshold slope is also comparable (see Figure 2).

Characteristic	NMOS Access	NMOS Pull-Down	PMOS Pull-Up
V_TLin	0.23 V	0.32 V	-0.40 V
DIBL	~37	~29	~69
Sub-threshold slope	~87 mV/decade	~71 mV/decade	~80 mV/decade

The output characteristics for the NMOS and PMOS transistors in the Intel 22 nm SRAM transistors were obtained, for the gate voltage varying from 0 V to 1.1 V. For example, Figure 9 shows the NMOS pull-down transistor output characteristics. The I_DSAT values, with V_G=0.8 V and V_DS=0.8 V, are 0.56 mA/µm for the NMOS pull-down and -0.51 for the PMOS pull-up transistors.

Figure 9 NMOS Pull-Down Output Characteristics (Source: Chipworks/Multiprobe)

In conclusion, Chipworks was able to extract accurate DC characteristics at the 22 nm technology node. A full discussion of the results is available in our Transistor Characterization Report. Chipworks will continue to use the most accurate measurement techniques available to provide reliable electrical characterization to our customer base. Please watch our blog for an upcoming comparison of transistor characteristics on two functionally identical, dual-foundry sourced die.

References

[1] Stephen Doering, “Investigation on the Influence of Focused Electron Beam on Electrical Characteristics of Integrated Devices,” ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis

Related Chipworks Reports

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