A Peak Inside the Micron 1 Gb, 45 nm PCM
By: Rajesh Krishnamurthy
Phase change memory (PCM) combines the nonvolatile attributes of flash memories like NOR and NAND types, combined with the bit alterability and fast reads and writes of RAM or EEPROM. This positions PCM to potentially provide memory solutions in the memory subsystems of cellular phones, PCs, and embedded and consumer electronics applications. Micron (previously Numonyx) and Samsung have already previously demonstrated a NOR compatible PCM for commercial applications. However, Micron has previously never managed to manufacture dense PCM memory for mobile applications, even though in an IEDM 2009(1) paper, they demonstrated a 1 Gb PCM memory array with 0.015 µm2 cell size (5.5F2) using 45 nm generation PCM technology. In 2011, Samsung, the other significant player in bringing PCM technology to commercial products, managed to bring a NOR-compatible 65 nm PCM memory to market and used it in Samsung GT-E2550 GSM feature phones (analyzed previously by Chipworks(2)), though it was used in a limited number of phones. In early 2013, Micron has mass produced their next generation PCM intended for mobile phone applications, a 45 nm PCM which is a shrink from their previous 90 nm PCM. Unlike their previous generation PCM products and unlike Samsung’s NOR compatible PCM multichip package (MCP) consisting of PCM and UTRAM dies, this 45 nm Micron PCM is packaged in an MCP, uses an LPDDR2 interface, and shares the same memory bus between the LPDDR2-PCM and LPDDR2-SDRAM dies in the MCP.
Chipworks found Micron’s 1 Gb PCM chips in a low-end smartphone from Nokia, shown in Figure 1.
Figure 2 is a top-view photograph of the Micron PCM MCP on the main printed circuit board of the Nokia smartphone.
Figure 3 shows the top and bottom photographs of the MT66R7072A PCM-based MCP extracted from the Nokia smartphone.
The PCM MCP is a 121 ball FBGA package with package dimensions 11 mm x 10 mm x 0.9 mm (thick). A side-view X-ray image of the MT66R7072A PCM, shown in Figure 4, reveals that the PCM MCP is a 1 Gb LPDDR2-PCM die co-packaged with a 512 Mb LPDDR2 die.
Figure 5 shows the die photograph of the MT66R7072A PCM.
The PCM die is manufactured using three levels of Cu metal plus a top level of Al metal in a 45 nm BiCMOS process. Figure 6 shows an overview and detailed SEM cross section of the PCM, while Figure 7 shows SEM plan-view images of the PCM cell delayered to metal 1 running just above the phase change layer, contacts, and substrate diffusion. The Micron PCM has a cell area of 0.011 µm2 which is about 58% smaller compared to the 0.026 µm2 cell area for the Samsung 512 Mb PCM cell manufactured in a 65 nm BiCMOS process, or 90% smaller compared to the 0.10 µm2 cell area for the Numonyx 128 Mb PCM cell manufactured in a 90 nm BiCMOS process; both parts previously analyzed by Chipworks. This cell size reduction is more aggressive than what would be expected from just a process node shrink from 90 nm to 45 nm. The aggressive shrink in cell size is facilitated by adopting a vertical access device and arranging the memory cell in a 5.5F2 design. The 5.5F2 memory cell design includes wordline (access device base) contacts shared by four PCM lines. A PCM cell is placed at the intersection of PCM lines and wordlines. A thick STI separates wordlines while a thin STI separates the adjacent emitters and the base contacts. The effective cell size of the 5.5F2 memory cell will be slightly larger than the equivalent 4F2 cross-point cell adopted by Samsung for their 65 nm PCM device. Micron claims in an IEDM 2009 paper(1) that the marginal disadvantage in the increased effective cell size is trumped by the significant reduction in the voltage drop on the wordline (base access) resistance.
Micron has taken a leading position in the scalable PCM technology with this MT66R7072A, produced in volume to be used in commercial smartphones. Volume production of high density PCM memory is a significant milestone, due to its simpler structure and significant cell size reduction. Samsung, the only other serious player with commercial PCM products, has demonstrated in a 2010 publication(3) further scaling of the PCM cell down to sub-20 nm technology (F=17 nm), by using the same overall approach of stacking PCM lines directly over the access device.
1. G.Servalli, “A 45 nm Generation Phase Change Memory Technology,” IEDM 2009, pg 113
3. I.S Kim et. al, “High Performance PRAM Cell Scalable to sub-20 nm Technology with below 4F2 Cell Size, Extendable to DRAM Applications,” 2009 VLSI Technology Digest of Technical Papers, 2009, pg 203