Contributed by: Jessica Topple email@example.com
Chipworks operates five labs, each with specialized expertise in reverse engineering. We use some commercially available equipment that is common in semiconductor labs and foundries but customize how it is used to meet the needs of reverse engineering.
This Inside the Lab takes a look at a specialized piece of equipment and how we employ it.
Scanning Capacitance Microscopy
- What is SCM dopant analysis and why do we need it?
- How does SCM work?
- What types of device can I apply SCM analysis to?
What is SCM dopant analysis?
SCM is a type of scanning probe microscopy (SPM) performed on an atomic force microscope (AFM). It produces a map of the doping type (n or p) with qualitative information about the carrier concentration present (more details below) in a semiconducting sample surface, with nano-to-micro scale resolution.
To fully understand how a semiconductor device is engineered, it is essential to know which dopant structures are formed and where they are located in the device. SCM can be applied to map structures such as source/drain implants, STI/DTI, epitaxial layers, photocathodes, diffusions, wells, etc.
What about other dopant profiling methods?
Other methods can provide complementary information on semiconductor dopant structures, but don’t offer the same 2 dimensional mapping as SCM.
- Silicon staining can be used to preferentially etch doped structures during sample preparation for scanning electron microscopy (SEM), which then allows for dopant structure identification. When using this method it is easy to over or under etch, making it generally less reliable and often more costly.
- Spreading resistance profiling (SRP) is commonly used for quantitative dopant profiling. This method has low spatial resolution (on the order of several tens of microns) and only provides information in 1 dimension. It measures carrier concentration (electrons or holes), not actual dopant atoms.
- Secondary ion mass spectrometry (SIMS) is used to profile the elements used to dope a semiconductor device. A relatively large area, on the order of 10 µm square is needed to obtain a good profile. Here we actually count the dopant atoms so it can give slightly different results from spreading resistance measurements.
How SCM Works
SCM measurements are taken while simultaneously performing contact mode AFM imaging to map topography. The dopant-related SCM data is obtained by applying an AC tip-sample bias and locally measuring the differential capacitance (∂C/∂V) at each pixel of the image.
- The phase of this signal depends on the charge carrier type; electrons or holes, and therefore indicates whether the material below the tip is n-type or p-type.
- The amplitude of the SCM signal depends on the thickness of the depletion layer formed in the sample below the AFM tip, which depends on the local charge carrier concentration and on the tip-sample junction geometry. This would require in depth modeling and calibration to extract the quantitative dopant concentration, and is therefore a qualitative representation of dopant density, complimented by quantitative SSRM (scanning spreading resistance microscopy) profiling.
- A single image scan simultaneously maps both the surface topography and the SCM dopant distribution.
What does Chipworks’ SCM reveal?
The figure below shows an SRAM sample imaged by silicon-stained SEM (left) and SCM (right). This SRAM sample was prepared by beveling the surface to expose columns of programmable logic cells. In the images we see that the silicon stain allows some differentiation of n and p type, but the SCM image reveals substantially better dopant structure identification and higher detail resolution.
What do the colours indicate?
Blue corresponds to p-type doping, yellow corresponds to n-type doping, and pink corresponds to regions where the SCM signal is weak.
A weak SCM signal occurs in two extreme cases: the depletion region between tip and sample is either too thin or too thick to observe charge carrier modulation, corresponding to either highly doped or low/undoped material respectively.
The SCM signal can be deconstructed using a lock-in amplifier. In the figure below, SCM signal amplitude is shown on the left and phase is shown on the right – corresponding to qualitative dopant concentration and dopant type (n or p) respectively.
Look closely and compare these images with the SCM image in the figure above – structural details may be more easily observed by viewing these signals separately. The faded region in the middle is due to oxide wear from previous smaller ranged images – and influences amplitude, but not phase.
Surface topography is simultaneously mapped during SCM scanning, as shown in the figure below. This scan was performed further down the bevel, and the doped structure feature transition is apparent.
Topography may be displayed on its own (left) or 3D rendered with the SCM signal overlaid (right) for a better impression of how to visualize samples.
Why SCM is Useful
Identifying n and p type doped areas is fundamental to interpreting the process technology employed in a semiconductor device. When combined with other analysis techniques (such as scanning and transmission electron microscopies), SCM lets readers of Chipworks’ reports understand the innovation at work. Reports are typically used for several reasons:
SCM to help find and document patent infringement
When enforcing a structural (also called “process”) patent related to, for example, the design of a capacitor over a well or the design of a diode, SCM can be used to spatially characterize doped structures present in the device in order to identify infringement and document the evidence. It is not generally sufficient to produce a claim chart that implies functionality during a multi-million dollar licensing negotiation. The direct evidence of SCM mapping may be used to validate functional claims by demonstrating/determining/establishing/revealing the type and location of specific dopant structures.
SCM to help enable circuit extraction
Extracting a chip’s circuitry (or a block thereof) requires the assembly of a floor plan that can be comprised of thousands and even tens of thousands of Scanning Electron Microscope images per layer of the chip. However, the contrast mechanisms of such imaging techniques are not always sufficient to identify all of the specific device types present. For example, while an optical image can indicate the presence of a bipolar transistor on a power device die, only SCM can reliably determine whether it is npn or pnp. Such dopant-related details provide a more complete picture of device structure to enable circuit extraction. These structural details further allow for a better understanding of device functionality and more accurate simulation of circuit performance.
Stay tuned for a series of “Inside the Lab” blog posts on related scanning probe microscopy modes such as magnetic force microscopy (MFM), along with TEM analysis, ion etching technology, and more.
- C.C. Williams “Two-dimensional dopant profiling by scanning capacitance microscopy”, Annual Review of Materials Research, 29 (1999), 471–504
- Takasaki, T. Yamamoto, “Cross-section analysis of electric devices by scanning capacitance microscope”, ESREF99, (1999)
- G. Zimmermann, A. Born, B. Ebersberger and C. Boit, “Application of SCM for the microcharacterization of semiconductor devices”, Applied Physics A: Materials Science & Processing, 76, 6 (2003), 885-888
- Lau, Y.M. Lim, V.S.W. Ang, L.B. Trigg, A., “The application of scanning capacitance microscopy in device failure analysis [doping profile determination],” Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, 99- 102, 5-8 July 2004
- Y. Naitou; A. Ando, H. Ogiso, S. Kamiyama, Y. Nara, K. Nakamura, “Spatial fluctuation of dielectric properties in Hf-based high-k gate films studied by scanning capacitance microscopy”. Applied Physics Letters, 87 25 (2005), 252908–1 to 252908–3
- Hung Sung Lin, Wen Cheng Shu, “Using a combination of C-AFM and SCM for failure analysis of SRAM leakage in CMOS process with the addition of a DNW module,” 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, 37-40, 6-10 July 2009