Sony has twins, with more on the way!

contributed by Ray Fontaine, Process Analyst

In February 2008, Sony announced their initiative to launch two 5 Mp, 1.75 µm pixel generation CMOS image sensors (CIS).  We’ve done a full analysis on one and recently took a peak at the second.  The IMX024 is a 1.77 µm pixel sensor for an HD camcorder, while the IMX034 is a 1.75 µm pixel sensor for a camera phone (Figure 1).

Figure 1 – Sony 1.77 µm and 1.75 µm pixel size sensors

I’ll talk about the twins in a minute, but first it is worth mentioning the CIS pixel roadmap.  Recently we’ve seen 1.4 µm pixel CIS products announced from Aptina, OmniVision, Kodak, and Samsung.  While no official announcements have been made, companies such as STMicroelectronics have successfully demonstrated pixels at these dimensions.  In Figure 2, Sony indicates that they too have a 1.4 µm pixel system-on-chip (SoC) sensor in production.

Figure 2 – Sony 1.4 µm Pixel Production

So we can see where the innovators are going, but I would like to now talk about the waypoints on the journey to the 1.4 µm pixel.  As always, it helps to follow the money.  Designing smaller pixel sensors with increased performance is a costly endeavor.  Remember the days of building a CIS using a mature process line?   Well, there is a general correlation between pixel scaling and the need for a more advanced technology generation for production.  Naturally there is some industry aversion to investing in the 1.4 µm pixel generation until every bit of performance is milked from existing pixel designs.

That is exactly what we saw in the sensors we analyzed in 2007.  Companies such as Micron and OmniVision underwent 2 and 3 rounds of optimizing their existing pixel architectures.  These iterations were evolutionary in nature; sharing pixels, optimizing the metals for optical symmetry, thinning the dielectrics over the pixels, etc.  These iterations were pushed out to the market as same size pixel sensors with improved performance.

This brings me back to the Sony twins.  They’ve taken the design evolution approach one step further by optimizing based on end application.  Figure 3 shows the color filter array from the IMX024.  The IMX024 is a 5.6 Mp, 1.77 µm pixel CIS extracted from a Sony HDR-SR11 HD camcorder.  The conventional Bayer patterned color filter array is scrapped in favor of Sony’s ClearVid pixel architecture.  This architecture features a 45° pixel arrangement and a 1:6:1 RGB color filter array.  The increased green pixel count equates to higher sensitivity.  This novel pixel layout does require specialized image processing to interpret the captured image.

Figure 3 – Sony IMX024, ClearVid Pixel Layout

Figure 4 shows the metal 1 patterning used in the pixel array.  This clever metal 1 layout not only facilitates all of the necessary electrical connections, but also includes dummy metal patterns to provide a nearly symmetrical back end structure. 

Figure 4 – Sony IMX024, Pixel at Metal 1

While the IMX024 is optimized to handle HD video, its IMX034 sister is bred for capturing still images in a much smaller product.  Figure 5 shows the back of the SO905iCS camera phone, home of the 1.75 µm pixel twin.

Figure 5 – Sony SO905iCS Camera Phone

While the packaging for the IMX024 wasn’t worth mentioning, the IMX034 uses a fairly elaborate camera module.  A “periscope” system is used to stuff the lenses and focusing mechanism into the phone while maintaining a reasonable form factor (Figure 6).

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Figure 6 – Sony IMX034 Module

The IMX034 uses a conventional Bayer patterned RGB color filter array.  To date we have only performed a bevel analysis of the pixel array (no cross sectioning).  Figure 7 shows the orthogonal metal 1 layout including the outline of the light pipe window used over the photocathodes.  The IMX024 also used a unique light pipe structure, but that is the subject of another blog. 

We have only presented the metal 1 layout for each, but of course both sensors use their own flavor of pixel architecture.  In short, you might call them fraternal twins.  Sony has the advantage of designing sensors for their own products and as such we see a synergy between the downstream products and pixel/module designers.

 Figure 7 – IMX034 at Metal 1

In addition to Sony’s two pronged attack at the 1.75 µm pixel generation, they’ve also announced their production of a full frame CIS for DSLR applications.  This will be a first for Sony, and will be featured in their 25 Mp “Flagship” DSLR.  We wonder if the new sensor will be an evolution of their IMX021 pixel shown in Figure 8.  This was an APS-C size sensor taken from an Alpha 700.

Figure 8 – Sony IMX021 CIS from Alpha 700

Finally, putting together this blog has been interesting timing as Sony has just announced their development of a backside illumination (BSI) sensor.  Figure 9, taken from the Sony press release, shows a cross sectional view of their planned 1.75 µm BSI pixel structure.  OmniVision recently presented their OmniBSI™ architecture, while STMicroelectronics, MagnaChip, and others have also demonstrated the technology.  While this concept is not new the application should certainly prove to be disruptive and it is great to see new solutions to the shrinking pixel problem (signal-to-noise).  Sony has been one of the top innovators in the CIS game, and we look forward to a product announcement using this exciting technology.

Figure 9 – Sony Backside Illumination Sensor 

Links used:

http://www.sony.net/SonyInfo/IR/financial/fr/viewer/Semiconductor/2007/

http://www.chipworks.com/seamark.aspx?sm=s4%3BDatedfl10%3BDeviceType17%3BCMOS+Image+Sensorfl10%3BReportCode12%3BIPR-0804-801&cw=detail

http://www.sony.net/SonyInfo/News/Press/200801/08-010E/index.html

http://www.engadget.com/2008/02/01/sony-25mp-full-frame-dslr-hands-on/

http://www.sony.net/SonyInfo/News/Press/200806/08-069E/index.html

http://www.ovt.com/data/newsreleases/english/BSI%20Technology%20launch%20release_FINAL.pdf

MEMS Microphones Grown up and Making a Living

Contributed By: Kevin Gibb and Sinjin Dixon-Warren

We first observed MEMS based microphones back in 2003 when we did a circuit analysis of the Emkay (now Knowles Acoustics) SP0103 microphone. The field seemed pretty quiet until 2007 with our teardowns of cell phones consistently yielding coil type microphones.

The situation started to change in January 2007, when we found an example in what we believe is one of the early adopters of MEMS microphones, namely Fujitsu with its F903i cell phone. In that case, we found the S575B MEMS microphone from Knowles. Adoption seems to have started in earnest sometime around the end of 2007 as the number of cell phones showing up in our labs, sporting Knowles microphones started to rise (Figure 1 and Table 1).

Figure 1 Cell Phone Models with Knowles Acoustics Microphones

Table 1 Makes and Models Using Knowles Microphones

Given the recent socket wins by Knowles; we thought it would be interesting to take another look at their microphones, in particular the SP103BE that we analyzed in 2006.

The package photographs are shown in Figure 2.  The resin reinforced fiberglass package (likely FR4) has a central cavity into which the MEMS microphone and amplifier die have been placed.  The ASIC has been covered by a gob-top type epoxy to protect it from the environment, while the Microphone die is left exposed.  The acoustic port to the outside world is seen just above the microphone.

Figure 2 Package Photographs

The microphone is made as two parallel capacitor plates, so it would seem that it would be quite sensitive to stray electric fields. Something clearly recognized by Knowles as they have lined the inside of the package with a metal film to form a Faraday cage (electrostatic shield). This metal film can be seen in the package x-ray (Figure 3).

Figure 3 Package X-Ray

The microphone itself has a quite simple design, comprising of two parallel polysilicon plates separated by a small air gap. The upper plate (poly 2) is perforated with an array of small holes(which are needed for the MEMS release etch). A solid poly 1 plate forms the bottom capacitor plate (Figure 4).

Figure 4 MEMS Microphone

One would think that replacing the coil or condenser microphone and its complex connecting wires, in favor of MEMS based microphones in surface mount packages would simplify the cell phone manufacturing, and perhaps lower their build costs. This has encouraged others to enter the MEMS microphone business, including MEMSTech, Infineon, Akustica, Sonion and others, in addition to Knowles who presently, according to Yole Developpments, dominate this market space.

MEMS by the Sea – It’ll be a Rough Trip!

contributed by Dr. Sinjin Dixon-Warren

As part of our ongoing interest in MEMS devices, Chipworks is participating in the 2008 Hilton Head Solid State Sensors, Actuators and Microsystems Workshop as a Corporate Sponsor. While we get all the altruistic benefits of supporting researchers and innovators in the MEMS industry, I will personally get the benefit of interacting with industry leaders in the famous collegial setting of Hilton Head. A number of companies including, SiTime, MEMSIC, Kodak, Hewlett-Packard, Analog Devices and Bosch will be presenting at Hilton Head and I am looking forward to hearing what they have to say about their next generation products, and explorative Research & Design. It is also impressive how the organizers of the conference were able to get such a nice cross-section of MEMS technologies on the agenda.

SiTime will be presenting the development of ultrathin packaging for the MEMS oscillator devices. It will be interesting to understand where they are taking in their existing industry-leading technology. It is likely that the ultrathin packaging is part of their strategy to target the consumer electronics market, especially mobile devices.

SiTime SiT8002AC Silicon Oscillator

MEMSIC will be presenting results on the development of a three-axis accelerometer, based on their novel thermal convection technology. We are currently looking at this device, reportedly fabricated at TSMC on a high volume process.  So far, it is certainly very interesting physically and I am itching to find out the engineers viewpoint on the benefits of this technology versus capacitance-based devices. I am especially hoping for some performance comparisons and some interesting discussions about the benefits of an accelerometer than can handle 50,000 g’s.

MEMSIC MXD6125Q thermal accelerometer

Gilbert Hawkins of Kodak will be giving an invited talk discussing the application of instabilities in microfluidic jets in digital offset-class ink jet printers. One would think that instabilities are undesirable, so if Kodak are actually using them to enhance inkjet printing, it could be a new tweak on the technology.  We actually looked at a 6J2032 Printhead last year, so we could learn a bit more about the detail of its operation from this paper – microfluidics is not exactly our specialty.

Kodak 6J2032 Printhead Heaters and Power Transistors

Hewlett-Packard (HP) is presenting three papers, plus the Biomedical Application session is being chaired by Peter Hartwell of HP. The first concerns the use of a microlens scanner in optical interconnect, the second concerns viscous damping of a MEMS device in a cavity, and the third concerns direct printing of PZT (lead zirconate-titanate) films. The range of these papers demonstrates the continued depth of Hewlett-Packard research, suggesting that this is a company worth watching.  The viscous damping paper could shed some light on the contents of the closed cavity that MEMS is placed in.  We usually analyze the gases therein, and sometimes it’s a bit of a mystery why they are there – one part had a mixture of sulfur dioxide (SO₂) and moisture, which is quite an acidic environment.  I know SO₂ is used to preserve wine, but in a MEMS?

Hewlett-Packard C9381A HP88 Printhead Microfluidic Layer

Not to leave out the poster sessions, which often have nuggets of gold that don’t make it to the conference proceedings. I’m looking forward to Analog Devices’ poster concerning the use of extrinsic gettering in SOI wafers in their MEMS fabrication. Until recently ADI’s iMEMS process did not use SOI, however, they have recently announced the use of SOI for their ADXL001 product.  The interest here is both ADI’s migration to SOI substrates, and the nature of the gettering process.   According to a recent Yolé report, the MEMS industry is going to take an increasing proportion of the thick SOI wafer production, so I guess we can look forward to more SOI-based MEMS.

ADI’s Stephen Bart, with Hermant Desai of Freescale, will also be co-chairing the Characterization session. As a Characterization specialist myself, I am particularly looking forward to this session, which kicks off with Gilbert Hawkins’ microfluidics paper.

Analog Devices ADXL330 Accelerometer Detail - No SOI!

Freescale MMA7455L 3 Axis Accelerometer

Last, but certainly not least, Bosch will be presenting both a paper and a poster on the subject of MEMS resonators. The paper discusses charge observations in MEMS resonators – we may have mostly solved charge problems in CMOS, but we are still characterizing it in the MEMS biz.  The poster is on mode matching in high Q gyroscopes.

Bosch is not only one of the grand-daddies of this industry, having developed the critical patented Bosch Etch DRIE technology (US Patent US5501893, 1996), but they also continue to deliver innovative products, particularly in the inertial sensor market space.

Bosch SMB380 3 Axis Accelerometer Detail 

So, despite the attractions of the location, it should be a fascinating few days; and if there are quiet spells, it leaves me with time to reflect and take in the sea air.

2008 - the year of the through silicon via (TSV)?

By Kevin Gibb

The market is abuzz with talk of TSVs, with market researchers, reverse engineering companies, consultants, and just about everybody on the hunt for their implementation in products.

Through silicon vias are a long time in coming; as one of our own engineers was involved in a TSV project some 11 years ago, and at that time it was deemed to be too difficult to make commercially viable and cancelled. Hopefully all of the noise we are hearing from manufacturers won’t take another 11 years (or even months) to happen.

The argument for TSVs is now compelling, as device integration and technology node shrinks are forcing engineers to consider 3D integration for some device sectors. We think cell phone CMOS image sensors will be the first to market with TSVs, followed by memories. Both get cost benefits on highly repetitive structures and both have been publishing papers, patents, and press releases faster than you can say, “wafer scale packaging”.

CIS will very likely precede NAND or DRAM since technical requirements on the TSV's will be less stringent for CIS packaging. Memory will be very close behind (probably Samsung) since they are investing more in development and reap better overall benefits as a percentage of the total cost of manufacturing. Chipworks' bet is on Toshiba delivering an image sensor, because they already claim to be in production with a VGA CIS with TSV's. However, it has not shown up in a downstream mobile phone yet.

With this in mind, we thought it a good time to take a look at some of the interesting multi-chip packaging that we have seen that help to get us to this point. The two good reasons for this are because it helps illustrate some of the challenges, but also because the images are just, well, cool.

A few years ago a Sharp device came out with a five stack chip scale package containing three flash and two SRAM dies stacked one on top of the other. The full package measured 8mm x 11 mm and only 1.13 mm thick. To a large extent this was achieved by thinning the dies down to an average of 95 µm thick each. This seems quite impressive as many single dies are still, even today, packaged with a 200 to 250 µm thickness.

Figure 1 Sharp 5 Stacked Chip SRAM & Flash Memory

Sharp was not alone with this strategy, as Fujitsu was also offering a multichip package having two flash, an SRAM and DRAM dies in a 11 mm x 12 mm by 1.1 mm thick package. Again thinning of the dies was in order, but to only 130 µm thick in this case. We also note the horizontal approach of the wire bonds to the top die (die 4).

Figure 2 Fujitsu 4 Stack Flash, SRAM and DRAM Memory

The wire bonding to the dies has also been modified to allow a near horizontal approach of the bond wires to the die. This permits a reduced loop height for the bond wires and consequently a thinner package. A seminal development for wire-bonding multi-stacked dies has been the ability to reverse the direction of the wire, first placing a stub ball bond on the die, then wedge-bonding the wire on to that.

The most remarkable example we have seen so far was in a Sandisk 8 GB memory which also had a five-stack (four 2 Gb/16 Gb die + a spacer) structure. As you can see we have a stub bond on the top die, with a wire wedge-bonded from that to a ball bond placed on a wedge bond from a lower wire, on another stub on the die below. And these bonds were on a die thinned to a remarkable 65 μm, and hanging out 750 μm beyond the spacer below!

Figure 3: Sandisk 8Gb Bonding

Real estate is still expensive in cell phones, with a push to shrink the footprint for every IC being used. One strategy for achieving this is to dispense with the bond wires and use some form of chip scale package interconnects.

Shellcase did this almost a decade ago with their chip scale packaging for CMOS image sensors. This approach puts the package interconnects on the backside of the die, so that the entire package can be flip-chip bumped to a printed wiring board. This approach seems successful as OmniVision has adopted this approach for their OV2640 CMOS image sensors being used and Sony Ericsson's V630i mobile handsets. In this case XinTec appears to have provided the packaging for OmniVision.

Figure 4 Chip Scale Package for a CMOS Image Sensor

And this leads us to the next idea for reducing the package size, and that is to use TSVs. The idea is to allow dies to be stacked one on top of the other, with the interconnects feeding from one die to the next through stacked die vias.

Of course the GaAs guys are probably wondering what all the fuss is about, as they have been producing die with TSV’s for the past 10-15 years. With GaAs being an insulating substrate they are needed to ensure a good ground plane and to remove heat from the die. The example below from Philips is a GaAs HBT power transistor contained in a small GSM power amplifier. The GaAs has been thinned to about 75 µm thickness, after which the 70 µm wide vias have been etched from the backside. As is normal with GaAs TSVs, the vias are plated with gold.

Figure 5 Through Hole Via in Philips GSM Quad Band Amplifier

Whether TSVs show first in CMOS image sensors or memories, we can be sure that they will be leveraging the work that the MEMS industry has done in dealing with deep-etched silicon structures. TSV’s will almost certainly be etched with some derivation of the common “Bosch” etch process. A paper at this weeks ASMC conference from Puech et. al. of Alcatel Micro Machining Systems gave a good description of the etch technology required for TSV. We have an example below from SiTime, which has used a Bosch etch to form the ring of trench isolation (annulus) surrounding the polysilicon via shown in Figure 5. Not quite a TSV but certainly a very deep silicon via relative to the width.

Figure 6 SiTime Polysilicon Via

Intel Atom to be Analyzed

Contributed by Dick James, Senior Technology Analyst

Chipworks has the Intel Atom processor in our labs, and we will be looking at it in detail over the next few weeks. Since Intel has announced [1] that it is made with the same process [2] as the Penryn, we will be looking for differences rather than doing the type of exhaustive analysis that we did on the Penryn.

We will be looking first at the front-end processing and the dielectric stack to confirm the high-k/metal gate structure. We’ll also examine the interconnect stack, the SRAM cell layout and size, and logic cells – in other words, anything that could contribute to the low-power designation of the chip.

Just looking at the chips as we received them, it’s obvious that they are low-power parts – no honking great heat spreader such as we saw on the Xeon version of the Penryn. The Atom is on the left below; of course the scale is different, since the Xeon package contains two 105 mm² dice on a 37.5 x 37.5 mm board, whereas the Atom is ~25.5 mm² on a 13 x 14 mm substrate.

The first thing I wondered, when I heard that we had the Atoms, was whether the thick copper redistribution layer (RDL) used in the Penryns was still used. After all, low power means reduced current, and if the current is reduced, is a thick copper layer needed?

The first sight of the naked chip cleared that up – see the die photo below. If you squint hard, you can see what look like micro-tracks, which are actually the gaps between the wide redistribution lines.

We can see them more clearly in the die marking image:

This RDL is ~6.5 µm thick, and appears to be electroplated on to a thin Cu seed layer. This is from our Xeon report:

According to Intel, this layer is used for improved on-die power distribution, which in a part that dissipates ~2W rather than >60W seems a bit like overkill. On the other hand, there will be side benefits such as good thermal redistribution across the die, and having these thick, wide copper tracks on the chip surface must help the layout and alignment of the copper bumps used by Intel these days to connect to the outside world. This is what the stack looked like in the Xeon:

We’ll comment more on the Atom itself when we’ve finished the analysis.

In the meantime, Digitimes speculates that Asus has ordered 2.5 – 3 million Atom chips from Intel for the new version of the Eee to be launched in June, and Acer has ordered another million.

Via Technologies also seems to be getting a boost from interest in mobile PC chips – HP is reported to have ordered ~100k Via C7-M low-power processors for its HP 2133 Mini-Note PC. They also got a boost from a German Eee website with a comparison test showing that the new Via Isaiah chip handily outperforms the Atom.

We’ll see what happens with the Atom – there is viable competition out there, and it is likely to increase, as the mobile internet is perceived as the growth market for the next few years.

[1] G. Gerosa et al., A Sub-1W to 2W Low-Power IA Processor for Mobile Internet Devices and Ultra-Mobile PCs in 45nm Hi-κ Metal Gate CMOS, 2008 IEEE International Solid-State Circuits Conference, pp 256-257.

[2] K. Mistry et al., “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging”, 2007 IEDM Tech. Dig. pp 247-250.

A Shameless Plug for ASMC

Winter is finally starting to fade in Ottawa, after one of the snowiest winters in memory (the first white Easter in my time here!), and the early signs of spring are showing. The maple sap is running, the first migrant birds have arrived, the frogs are peeping, and we have evening daylight. On the conference calendar, spring means that ASMC (Advanced Semiconductor Manufacturing Conference) is on the horizon, this year in Cambridge, Massachusetts. There, spring in early May should be well advanced, and it will be a great time of year to visit New England.

As the name says, ASMC is an annual conference focused on the manufacturing of semiconductor devices – in this it differs from other conferences, since the emphasis is on what goes on in the wafer fab, not the R&D labs, and the papers are not research papers.

I’m plugging ASMC because it seems to be one of the more under-rated conferences, unlike IEDM and the VLSI symposia which get the media attention for leading-edge R & D and processes. However, it’s the nitty-gritty of manufacturing in the fab that gets the chips out of the door, and this meeting discusses the work that pushes the yield and volumes up and keeps them there.

I always come away impressed by the quality of the engineering involved; not being a fab person myself any more, it’s easy to get disconnected from the density of effort required to equip a fab, keep it running and bring new products/processes into production. Usually the guys in the fab only get publicity if something goes wrong!

This year there are more than 80 papers, with keynotes from AMD, IBM, Intel, Linde Electronics and Synopsys. Sessions include:

• Advanced Metrology
• Advanced Processing
• Advanced Equipment and Materials
• Contamination Free Manufacturing (CFM)
• Cost Reduction, Equipment Reliability and Productivity
• Defect Inspection and Reduction
• Design for Manufacturability (DFM)
• Factory Automation and Dynamics
• Lithography Advances
• Yield Methodologies.

Of course, I’m biased to some extent because I’ll be giving a paper there – “From Strain to High-K/Metal Gate – the 65 – 45 nm Transition”, essentially a review of transistor structures from the 65-nm generation through to the Intel 45-nm chip. This will be the fourth year running I’ve given a paper there, the manufacturing and equipment engineers that attend seem to like seeing what other companies are doing.

Last year we also had a good range of topics - there are a lot on esoteric (for me, anyway!) stuff such as fab loading algorithms and yield modeling, but there are also nuggets of information in the processing area.

An interesting bit of diagnostic work that stuck in my mind was an instability in voltage references in a SOI-based microprocessor caused by mobile charge contamination [1]. The process includes tungsten local interconnect, and of course the interconnect trenches were cut through the CESL nitride; however, where these openings overlap onto isolation oxide, there are entry points for mobile ions, which can then migrate into the buried oxide underneath a transistor, affecting the body potential.

Apart from removing the cause of the contamination (not easy with some process steps!), the mechanism can be eliminated by keeping the tungsten over active silicon. This problem struck a chord in me, mainly because it was something that I hadn’t thought about, but is quite logical since SOI devices are by definition surrounded by oxide.

We tend to forget that mobile charge was the curse of MOS technology in the early days, to the point that people weren’t sure that it could be made to work at all. Bruce Deal wrote a great review paper of the problems way back when in ’74 [2], and he included this telling cartoon by Bob Donovan that aptly summarizes the confusion that existed before we finally got a handle on the different types of oxide charge.

I guess I drifted a bit off topic there, since that was a bit of a trip down memory lane, and not much to do with ASMC – but if you’re in the market for real-world fab information, compared with R&D exotica, come to Cambridge next month. I look forward to meeting you!

[1] M. Connell et al., “Impact of Mobile Charge on Matching Sensitivity in SOI Analog Circuit,s” Proc. ASMC 2007.

[2] B. E. Deal, “The current understanding of charges in the thermally oxidized silicon structure,” J. Electrochem. Soc., vol. 121, p. 188C, 1974.