Intel’s Other IEDM Paper – Part 2

Dick James, Senior Technology Advisor

Last week we looked at the lithography improvements in gate patterning, particularly in the SRAM array. This week let’s take a broader look at other improvements in lithography and layout seen in the 45-nm process, since Intel has stayed with dry exposure when others are moving to wet lithography tools. Table 1 lists the pitches of the different levels that we found in our analyses.

Table 1 Pitch Measurements in Intel Xeon and Yonah

Figures 1 – 4 show images of the SRAM array from the Xeon (left), and the 65-nm Yonah chips, going down from the metal 3 (M3) level to the gate level. At all the metal levels we can see that, contrary to intuition, the edges are much crisper and line edge roughness is reduced. (In the Xeon-M2 sample, there has been some movement of the lines due to our sample prep.)

Figure 1 Plan-View SEM Images of M3 Level in Intel Xeon and Yonah

Figure 2 M2 Level in Intel Xeon and Yonah

Figure 3 M1 Level in Intel Xeon and Yonah

Figure 4 Gate Level in Intel Xeon and Yonah

In the gate images (Fig. 4), the edges are not as well defined, but then the sidewall spacers are also present – we cannot see the actual gate edges. The tungsten M0 level is also present in the Xeon sample to add to the confusion. The Intel images (see last week’s blog) of polysilicon from the IEDM paper are clearer, and show similar impressive changes.

When it comes to the metal levels, at M1 it seems that dual-APSM has been used (double masking as opposed to double patterning). Fig. 3 shows the “wiggle” in the V_DD line, and Figure 5 shows an area of standard cells in the logic array, with some very tight Manhattan layout in the cells. It was in these areas that we found the tightest M1 pitch, closer to 150 nm than the announced 160 nm [1].

Figure 5 Plan-View SEM of Metal 1 in Logic Area

With features this densely spaced, and using dry exposure tools, it is obviously a daunting task to define patterns without any faults, even with APSM and the most advanced reticle enhancement and optical proximity correction techniques. Dual APSM takes the hypothesis that phase conflicts can be avoided for both masks, if apertures oriented along the vertical direction are assigned to one mask, and those along the horizontal direction to the other [2]. If Intel is using dual-APSM, I think the hypothesis is proven!

At M2, we found a very limited use of orthogonal patterning, and M3 none at all; but since the pitch is still 160 nm, it is possible that dual masking was used, although the M3 masks would be oriented in the same direction.

If we look again at Fig. 5, we can see that some of the lines between the logic cells are a darker shade of grey than others in the cells. This is a function of the secondary electrons seen by the SEM detector, but for our purposes it indicates dummy metal lines used in the layout of the part. The same effect is shown (Fig. 6) at M2 and M3. In other parts of the die Intel has used dummy metal for a much greater proportion of the area, particularly at the M1 level (Fig. 7).

Figure 6 Plan-View SEM of M2 (right) and M3 in Logic Area

Figure 7 Dummy M1 and Interconnect

Of course, the use of dummy metal is almost as old as the use of CMP, but this is the first time we have seen it employed so extensively, so densely, and so early in the back-end processing. For CMP control we usually see small structures such as squares of metal– here the dummy structures are lines squeezed in at every possible position where there is no active metal needed. However, the regularity of this layout cannot but reduce the lithographic variation, and coupled with CMP improvements (Fig. 8), we get the impressive metallization seen in Figs 1-3.

Figure 8 Improvement in M1 Uniformity after Cu Etch and CMP Enhancements [3]

We also found the same layout philosophy used at the gate level. Figure 9 is an example of an area of general logic (note that the diffusions are covered by dielectric material in this image). Repetitive columns of metal gate fingers are arranged parallel to columns of M0 trench contacts. In regions where no active devices are required, these metal gate strips serve as dummy structures. Where an active device is required, the column is simply broken, long enough to form a gate finger, and continues on again beyond the device as dummy metal. In the same way, the W trench contacts can be tailored to any length necessary.

Figure 9 Gate-Level Image of Logic Area

This layout has several advantages; in addition to aiding lithography, the use of trench contacts also enables flexibility in choosing where to place a contact up to metal 1. The trenches can be routed to a region over STI to form a contact land, as opposed to being forced to contact the top of a conventional contact stud over active Si.

The trench contacts also form butted, or split, contacts enabling connection of one or several gates to one or several diffusions, without the use of a metal 1 strap. Numerous manufacturers have used butted contacts as a means to reduce the unit 6T SRAM cell size, but the Penryn die marks the first time we have seen Intel use butted contacts to increase packing density in the core logic blocks.

Intel had mentioned this “dummification” technique in a presentation at their 2006 Developer Forum [4], and in addition to the above advantages, they claim that it reduces leakage (Fig. 10) and improves thermal processing (Fig. 11). This makes intuitive sense, since more uniform metal density across the die and across the wafer should improve the uniformity of heat absorption and dissipation, and thus reduce any hot or cool spots that could affect dopant variations.

Figure 10 Performance Improvements after Dummification [4]

Fig. 11 Process Parameter Improvement after Dummification [3]

To monitor the end-of-line results, Intel designers place ring oscillators in all product designs. Performance data such as f_max can be used to identify areas of concern, and give a measure of the systematic and random variation seen in the process. Figure 12 shows the trend in f_max over recent process generations: looking at this, it is apparent even after four generations of shrinkage, variation is amazingly well controlled.

Figure 12. Trend in Systematic Within-Wafer Variation from Ring Oscillator f_max Data [3]

So to wrap up, while Intel’s process paper [1] got all the advance hype, Kelin’s paper [3] reveals an equally impressive and detailed body of work, and equally essential to the manufacturing success of the 45-nm products.

Judging by the limited sample seen in our analyses, all the work done on improving individual process steps, and using the kind of design and layout changes discussed above, paid off admirably in the final product. A true tribute to the 45-nm development and manufacturing team!

References:

[1] K. Mistry et al., “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging”,Proc IEDM, 2007 pp. 247 – 250; http://download.intel.com/technology/IEDM2007/HiKMG_paper.pdf; http://download.intel.com/technology/iedm2007/HiKMG_pres.pdf

[2] D. Bernard et al., “Clear-field dual alternating phase-shift mask lithography” Optical Microlithography XV, Proc. SPIE Vol. 4691, p. 999-1008.

[3]K. Kuhn, “Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS”, Proc. IEDM, 2007, pp. 471 – 474;http://download.intel.com/technology/IEDM2007/variation.pdf,http://download.intel.com/technology/IEDM2007/variation_pres.pdf

[4] S. Rikhi et al., “Design for manufacturing”, IDF 2006, session EPRS008

N.B. This blog is excerpted from this months “Chip Forensics” article in Solid State Technology magazine.