2008 - the year of the through silicon via (TSV)?

By Kevin Gibb

The market is abuzz with talk of TSVs, with market researchers, reverse engineering companies, consultants, and just about everybody on the hunt for their implementation in products.

Through silicon vias are a long time in coming; as one of our own engineers was involved in a TSV project some 11 years ago, and at that time it was deemed to be too difficult to make commercially viable and cancelled. Hopefully all of the noise we are hearing from manufacturers won’t take another 11 years (or even months) to happen.

The argument for TSVs is now compelling, as device integration and technology node shrinks are forcing engineers to consider 3D integration for some device sectors. We think cell phone CMOS image sensors will be the first to market with TSVs, followed by memories. Both get cost benefits on highly repetitive structures and both have been publishing papers, patents, and press releases faster than you can say, “wafer scale packaging”.

CIS will very likely precede NAND or DRAM since technical requirements on the TSV's will be less stringent for CIS packaging. Memory will be very close behind (probably Samsung) since they are investing more in development and reap better overall benefits as a percentage of the total cost of manufacturing. Chipworks' bet is on Toshiba delivering an image sensor, because they already claim to be in production with a VGA CIS with TSV's. However, it has not shown up in a downstream mobile phone yet.

With this in mind, we thought it a good time to take a look at some of the interesting multi-chip packaging that we have seen that help to get us to this point. The two good reasons for this are because it helps illustrate some of the challenges, but also because the images are just, well, cool.

A few years ago a Sharp device came out with a five stack chip scale package containing three flash and two SRAM dies stacked one on top of the other. The full package measured 8mm x 11 mm and only 1.13 mm thick. To a large extent this was achieved by thinning the dies down to an average of 95 µm thick each. This seems quite impressive as many single dies are still, even today, packaged with a 200 to 250 µm thickness.

Figure 1 Sharp 5 Stacked Chip SRAM & Flash Memory

Sharp was not alone with this strategy, as Fujitsu was also offering a multichip package having two flash, an SRAM and DRAM dies in a 11 mm x 12 mm by 1.1 mm thick package. Again thinning of the dies was in order, but to only 130 µm thick in this case. We also note the horizontal approach of the wire bonds to the top die (die 4).

Figure 2 Fujitsu 4 Stack Flash, SRAM and DRAM Memory

The wire bonding to the dies has also been modified to allow a near horizontal approach of the bond wires to the die. This permits a reduced loop height for the bond wires and consequently a thinner package. A seminal development for wire-bonding multi-stacked dies has been the ability to reverse the direction of the wire, first placing a stub ball bond on the die, then wedge-bonding the wire on to that.

The most remarkable example we have seen so far was in a Sandisk 8 GB memory which also had a five-stack (four 2 Gb/16 Gb die + a spacer) structure. As you can see we have a stub bond on the top die, with a wire wedge-bonded from that to a ball bond placed on a wedge bond from a lower wire, on another stub on the die below. And these bonds were on a die thinned to a remarkable 65 μm, and hanging out 750 μm beyond the spacer below!

Figure 3: Sandisk 8Gb Bonding

Real estate is still expensive in cell phones, with a push to shrink the footprint for every IC being used. One strategy for achieving this is to dispense with the bond wires and use some form of chip scale package interconnects.

Shellcase did this almost a decade ago with their chip scale packaging for CMOS image sensors. This approach puts the package interconnects on the backside of the die, so that the entire package can be flip-chip bumped to a printed wiring board. This approach seems successful as OmniVision has adopted this approach for their OV2640 CMOS image sensors being used and Sony Ericsson's V630i mobile handsets. In this case XinTec appears to have provided the packaging for OmniVision.

Figure 4 Chip Scale Package for a CMOS Image Sensor

And this leads us to the next idea for reducing the package size, and that is to use TSVs. The idea is to allow dies to be stacked one on top of the other, with the interconnects feeding from one die to the next through stacked die vias.

Of course the GaAs guys are probably wondering what all the fuss is about, as they have been producing die with TSV’s for the past 10-15 years. With GaAs being an insulating substrate they are needed to ensure a good ground plane and to remove heat from the die. The example below from Philips is a GaAs HBT power transistor contained in a small GSM power amplifier. The GaAs has been thinned to about 75 µm thickness, after which the 70 µm wide vias have been etched from the backside. As is normal with GaAs TSVs, the vias are plated with gold.

Figure 5 Through Hole Via in Philips GSM Quad Band Amplifier

Whether TSVs show first in CMOS image sensors or memories, we can be sure that they will be leveraging the work that the MEMS industry has done in dealing with deep-etched silicon structures. TSV’s will almost certainly be etched with some derivation of the common “Bosch” etch process. A paper at this weeks ASMC conference from Puech et. al. of Alcatel Micro Machining Systems gave a good description of the etch technology required for TSV. We have an example below from SiTime, which has used a Bosch etch to form the ring of trench isolation (annulus) surrounding the polysilicon via shown in Figure 5. Not quite a TSV but certainly a very deep silicon via relative to the width.

Figure 6 SiTime Polysilicon Via