Patent knowledge. Technology expertise. Market understanding.

Patent knowledge. Technology expertise. Market understanding.

Patent knowledge. Technology expertise. Market understanding.

DRAM Sub-Array Circuit Analysis Report

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With each new process generation, the basic DRAM cell shrinks, allowing more cells on a die and reduced costs for DRAM manufacturers. The top four DRAM suppliers (Samsung, Hynix, Elpida, and Micron) are the leaders in this cell shrinking.

The DRAM cells are placed in small blocks called arrays. Since the DRAM cells get both shorter and narrower, the blocks which drive the cells also need to get smaller with corresponding design optimization to compensate for loading and size.

 DRAM_die_photo

The DRAM Sub-Array Circuit Analysis Report extracts the schematics surrounding the core array of DRAM cells and delivers the report in the ICWorks Browser format. This standardized report focuses on one block to provide a cost-effective solution that delivers the critical information about the device. All circuits, in addition to pitch-matched circuits that are dedicated to a sub-array of DRAM cells, are included in this report. For example:

  • Each new smaller design of memory cells presents a different RC loading to the wordline drivers. This report shows the optimization of the WL driver pull-up and pull-down circuitry.
  • Each new smaller memory cell has a different capacitance and charge storage than the previous generation, and bitline designs have different R and C values. The sense-amps need to change at each generation to optimize the sensing of this miniscule charge shared across the RC of the bitline.
  • Change in architecture, such as from 8F2 to 6F2, results in partial arrays that are unusable. This report shows a partial array to see how this is managed.

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