Layout Analysis – Floor Plan
This report provides an overview of an IC’s die size, block sizes, and floor plan using detailed board, package, x-ray, literature, and layout analysis to name the functional blocks used on a chip. Clients use this information to compare their own designs and determine if their competitors use different or smaller functional blocks. This helps to allocate R&D resources, and to determine when further analysis, such as circuit extraction, is warranted.
These reports include the following detailed information:
- Package photographs
- Package x-ray
- Depot (bare die) die photo
- Die size measurements
- Annotated metal 1 or poly die photo showing the major physical blocks on the die
- Major layout blocks annotated
- Layout block measurements
- Table summarizing the length, width, area, and percentage die area of each block
- Total percentage of analog vs. digital vs. memory vs. I/O
