Layout Analysis – I/O
An overview of an IC’s I/O circuits. A lower level metal or poly die photograph is annotated showing the I/O blocks on the die. I/O cell type and size have a large impact on die size, and hence on product cost.
These reports include the following detailed information:
- Package photographs
- Package x-ray
- Depot (bare die) die photo
- Die size measurements
- Annotated metal 1 or poly die photo showing I/O groups (e.g., memory, host processor)
- Zoomed-in views of each analog block on the metal 1 or polysilicon layer
- I/O measurements
- Zoomed-in views of each type of I/O on the metal 1 or polysilicon layer
- Zoomed-in view of the die corner
- Zoomed-in view and measurements of pad size and pitch
- Discussion of possible functionality, bus type, and bus width of each I/O
- I/Os are identified with publicly available information (i.e., datasheets), signal tracing to on-board downstream products, and an engineering review of related Chipworks reports
- Table summarizing the length, width, area, and percentage die area of each I/O block
