We had decapsulated the A5 a couple of days ago, but as you could see in those early pictures, you can’t tell much of a chip’s layout from the top metal – it’s all power and ground buses. So we have to de-layer the chip down to a level where we can see the block layout of the chip; not an easy thing when there’s nine layers of metal! In fact, these days it’s easier to go in from the back and remove the substrate silicon, and look at the gate level from below. Then we can identify the circuit blocks that make up the full device.
Let’s look at the A4 to start:
The ARM core is at the bottom right, with an estimated 2.9 million logic gates and ~5.4 Mb of cache memory. We’ve labeled the other logic blocks to give an idea of what’s involved in the layout of one of these parts – so much do we take for granted these days!
And now the A5:
Here we’ve labeled the key blocks; the ARM cores are in the right half of the die, with ~4.5 Mb of cache memory each. We can also see the USB interface at the top, and the DDR SDRAM interfaces at the bottom right, for the memory in the top part of the package-on-package. Other I/O blocks are strewn around the edge of the die.
It seems likely that Apple will actually be shipping TSMC-made parts later this year, since Samsung is a competitor with its Galaxy tablet series. We’ll be watching and you can be sure that we’ll let you know when we find one.