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Patent And Technology Partner To The World's Most Successful Companies


IBM Continues to be a Major Source of Chip Innovation, Despite Rumours It May Exit the Business

Contributed by: Sinjin Dixon-Warren

IBM’s Semiconductor Division and Intel have been two of the primary drivers of advanced CMOS development for nearly fifty years. Although Intel has usually been first to market with a new technology node, IBM has continued to be a major source of innovation in advanced CMOS technology over the past decades. IBM achieves their impressive R&D record despite only having about $2 billion in semiconductor revenue, as compared to Intel’s $50 billion (source Gartner). One secret to IBM’s success is their partnerships with other major players. Despite rumours that IBM might exit the semiconductor business, IBM’s East Fishkill, NY, fab is one of the primary development centers, along with Albany Nanotech, for the Common Platform technology, a partnership between IBM, Samsung, and GlobalFoundries.

Chipworks has analyzed the evolution of IBM CMOS technology over the past decade. A particular focus for Chipworks has always been the transistor structure, which has become of increasing interest recently with the appearance of high-k metal gate (HKMG) technology.

IBM Power6 65 nm PMOS Transistor

IBM PPC970FX 90 nm NMOS Transistor   IBM PPC970FX 90 nm PMOS Transistor   Microsoft X02046 90 nm PMOS Transistor   IBM Power6 65 nm PMOS Transistor     IBM Power6 65 nm NMOS Transistor   IBM Power7 45 nm NMOS Transistor

The 90 nm IBM PPC970FX

The 90 nm IBM PPC970FX was analyzed by Chipworks in 2004. The 970 PowerPC family of chips was apparently the result of a short lived collaboration between Apple and IBM. The PPC970FX was built on silicon-on-insulator (SOI) wafers using a 12 metal process, including a single level of single damascene copper for metal 1 and nine levels of dual damascene copper for metals 2 through 10. A top aluminum-based metal was used for the bond pads, while a tungsten-based metal was used for metal 0 local interconnects. The active silicon SOI islands are isolated from the substrate by a buried oxide (BOX). Fluorosilicate glass, oxide, and nitride dielectrics were used for the back end of line (BEOL) process. Unlike the 90 nm offerings of other vendors at the time, carbon-doped low-k dielectrics were not used by IBM.

The transistors used on the PPC970FX were formed with polysilicon gates with a 0.35 µm contacted gate pitch (CGP). A nitride liner is used over the transistors and serves to provide tensile strain for the NMOS transistors to increase the electron mobility in the transistor channel. The NMOS sidewall spacer (SWS) was markedly thinner than the PMOS SWS, which further increased the strain applied to the NMOS transistors as compared to the PMOS transistors. The transistors were silicided with cobalt; however, no embedded epitaxial SiGe source/drain was used in the PMOS transistors, even though Intel had already introduced that technology at that time.

The 90 nm Microsoft X02046

The Microsoft Xbox 360 contained a customized IBM PowerPC processor, the X02046, which was designed jointly by Microsoft and IBM, and manufactured by IBM at their East Fishkill 300 mm foundry, using IBM’s 90 nm SOI technology. Curiously, at that time the processors used by the three main game manufacturers, Microsoft, Sony, and Nintendo, were all based on similar IBM technology. Chipworks published an analysis of the Microsoft X02046 processor in 2006. The X02046 was fabricated with a 10 metal process. The major difference between the X02046 and the PPC970FX was the introduction of dual stress liner (DSL) technology, where a tensile liner was applied to the NMOS and a compressive liner to the PMOS. In addition, the X02046 featured carbon-doped, low-k dielectrics.

The 65 nm IBM Power6

IBM continues to offer foundry services at 90 nm and 65 nm for bulk CMOS, and 45 nm and 32 nm on SOI and other speciality services; however, IBM retains its most advanced SOI technologies for their high-end Power server products. The processor chip in the IBM Power6 server analyzed by Chipworks was built using a 65 nm SOI process that featured dual stress liners to enhance both the PMOS and NMOS device performance. Eleven layers of metal with low-k dielectrics were used to fabricate the device. The transistors feature NiPt silicided polysilicon gates with a minimum contacted gate pitch of 0.25 µm, corresponding to the expected 0.7X shrink from the 90 nm node. NiPt silicide has a lower sheet resistance than CoSi. Again, we see no embedded SiGe in the PMOS devices.

The 45 nm IBM Power7

The IBM Power7 processor analyzed by Chipworks in 2011 was fabricated with a 45 nm SOI process. The process featured polysilicon gates with NiPt silicide. The major innovations, as compared to the 65 nm Power6, were the addition of embedded SiGe tubs in the PMOS source/drain (S/D) regions and the simplification of the transistor SWS structure. The SiGe applies additional compressive strain in the PMOS channels, which increases the hole mobility and further improves the transistor performance. The transistor contacted gate pitch was reduced to 190 nm, corresponding to a 0.76X shrink in the linear dimensions as compared to the 65 nm process. This is a slightly smaller shrink than the expected 0.7X scaling per node.

A major feature of IBM’s 45 nm SOI process was the addition of embedded DRAM. IBM claimed at the International Solid State Circuits Conference in 2007 that “with this breakthrough solution to the processor/memory gap, IBM is effectively doubling microprocessor performance beyond what classical scaling alone can achieve.” The embedded DRAM was based on deep trench capacitors in the silicon substrate.

The 32 nm IBM Power7+

IBM Power7+ 32 nm NMOS Transistor

IBM Power7 45 nm PMOS Transistor   IBM Power7 65 nm Embedded DRAM Cell   IBM Power7+ 32 nm NMOS Transistor   IBM Power7+ 32 nm PMOS Transistor

The Power7+ processor is IBM’s latest offering. They are built using IBM’s 32 nm SOI process including embedded DRAM. Chipworks has just completed a comprehensive analysis of the process, which features 14 layers of metal and gate-first HKMG transistors. The minimum contacted gate pitch is 130 nm, corresponding to a 0.68X shrink as compared to their 45 nm process. The process also features passive devices, including banks of trench capacitors and of metal-insulator-semiconductor (MIS) capacitors, plus diffusion resistors and metal inductors. IBM has continued to use the dual stress liner process to apply strain to the transistor gates.

The logic NMOS transistors used on the Power7+ processor were formed with high-k (HK) dielectric and a metal gate (MG) layer located beneath a conventional silicided polysilicon gate structure. The transistors were formed in a gate-first process, which means that the electrically active gate layers were deposited before the polysilicon gate structure and before the S/D engineering was completed. By contrast, Intel and TSMC use a gate-last process, as discussed in previous Chipworks blog postings.

The Power7+ PMOS transistors also feature a HKMG structure located beneath the conventional polysilicon gate. The metal gate material used for the PMOS transistors is tuned to adjust the work function. As discussed in a previous blog, the requirement for two different metal gates, with different work functions, is one of the major challenges for HKMG process technology. A thin layer of SiGe is used in the Power7+ transistor channel, which in combination with the work function tuned MG, optimizes the threshold voltage of the transistor. The SiGe also increases the hole mobility, which enhances the transistor performance.

The 32 nm technology used to fabricate the IBM Power7+ represents an extraordinary technical achievement. IBM continues to be one of the technology leaders in the global semiconductor industry, despite their #29 ranking in semiconductor total revenue (source Gartner). They are presently in the process of launching their 22 nm Power8 processor, with a contacted gate pitch of 100 nm [1], which is comparable to that found in Intel’s 22 nm finFET process, where the contacted gate pitch is 90 nm. IBM’s gate-first transistor technology has also been adopted by their Common Platform partners, Samsung (who fabricated the Apple A7) and GlobalFoundries.

IBM CMOS Technology Summary 02

[1] S. Narasimha et al., 22nm High-Performance SOI Technology Featuring Dual-Embedded Stressors, Epi-Plate High-K Deep-Trench Embedded DRAM and Self-Aligned Via 15LM BEOL, Proc. IEDM 2012 pp. 52-55.

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