Contributed by Dick James
Update (Oct 3rd) – Apple A7… and the Mystery of the Great SRAM Block
We said earlier that our floorplan was a best guess, and it was wise that we did – it appears that we got the L1 cache areas confused. Here’s the update:
As you can see, we’ve revised what we think was the L1 cache, as a result of going in to look closer with the electron microscope (optical microscopy hasn’t had the power for several generations, and now we’re at 28-nm there’s no other way). Again, we haven’t done any real circuit extraction – that would take months – so it is feasible that the other SRAM blocks visible in the core could form a more distributed L1 cache.
As part of the examination, we’ve also confirmed that the minimum SRAM six-transistor cell size is ~0.12 µm^2. This was used in the L2 cache and that huge SRAM block above the GPU cores. The L1 cache actually uses a slightly larger, ~0.15 µm^2 cell size, confirming some of the Twitter conversations that we’ve been having (@ChipworksDick), but it still comes out at 256 KB.
The Mystery of the Great SRAM Block continues, although we’ve now had a closer look at the relative areas of the memory blocks and support circuitry, and we’ve now upped the size to 4MB. Discussion continues at EETimes (and no doubt elsewhere), with opinions divided as to whether the SRAM is an L3 cache or some sort of cache or buffer for the GPU. (The block is strategically positioned next to both the GPU and a DRAM interface.)
Scorn was convincingly poured on my tentative theory that it might be used for fingerprint data, although I persist in believing Mr Ives in his video – if he says it’s stored in the A7, then I presume it’s stored in the A7.
Since there’s no NVM module that I know of in any 28-nm process (other than one-time programmable memory), then that data has to be stored in SRAM somewhere on the chip, even if it’s a small block of SRAM.
This is where Apple’s notorious reputation for un-reparability pays off. Since the battery cannot be removed, and the on-off switch just puts the phone into standby, then the phone is never off, the A7 is always powered, and so will be a dedicated block of SRAM. If the battery truly dies, my guess is that the fingerprint data will actually be lost. Anyone want to try it?
We have also been looking at the packaging; Apple’s suppliers have redesigned the package-on package (PoP) stack that has been used since the original iPhone way back in 2007. Specifically, the connections between the top memory package, and the lower section which houses the actual A7 chip have changed.
Here we have the memory package from an iPhone 5:
We are looking up at the bottom of the (top) memory part of the PoP. It’s a bit messy, because the solder balls have flowed a bit as we separated the two halves of the PoP.
The thing to note is the two rows of solder balls around the periphery of the package, which have a pitch of 0.4 mm. These are what connect the gigabyte of LPDDR2 memory in the top half of the PoP to the A6 chip itself.
Now if we look at the A7 memory package:
It’s immediately obvious that we have three rows of interconnect, with many more connections. Close examination showed that the ball pitch is now 0.35 mm, which doesn’t appear much of a reduction, but is definitely of note to those in the business.
And, with three rows, we now have a solder ball count of 456, up from 272 in the A6. I make that a 68% increase.
Which leaves us with a question – if there’s still only a gigabyte of memory up top (albeit LPDDR3 instead of LPDDR2), and it’s still 2 x 32-bit interface, why do we need all that extra interconnect?
Original blog post (Sep 27th)
After a thorough teardown of Apple’s iPhone 5s last week, we now have the transistor-level pic of the A7 and we can start to unravel what’s in it. Below is our tentative analysis of the A7.
We publish this with the caveat that these are best guesses – we have not done any real circuit extraction to confirm them. The dual-core CPU and cache make up ~17% of the die area, and the quad-core GPU and shared logic about 22%. The CPU itself is not packed the same way as the A6 (see below), it looks much more like a conventional automated layout; although Linley Gwennap thinks that it’s still Apple designed, not the first ARM A53/57 usage. There’s a great review of the A7’s capability over at AnandTech.
We know from our analysis of the 32 nm A6 chip that the 6 transistor SRAM cell area was ~0.15µm2, so if we shrink that, we can guesstimate the 28 nm 6T SRAM cell to be ~0.12 µm2. If we further allow a conservative 40%-50% utilization to allow for the row and column circuitry, then we get densities of ~1 MB for the L2 cache, and ~256 KB for the L1 cache.
When we look at the GPU, Anand also makes a convincing argument that the GPU is the four cluster version of Imagination’s PowerVR Series 6, the G6430.
One thing we haven’t identified is the memory block used for the data from the fingerprint sensor – Jony Ives, in his video about the sensor, clearly states that the information is stored securely in the A7 and emphasized it with this shot below.
One wonders if that huge block of SRAM (we make it ~3 MB) above the GPU cluster has anything to do with that . . .
Actually, if we compare it with the A6, that may not be such a stupid idea – there is no comparable block that I can see in there. I wouldn’t have thought that a fingerprint scan would create that much data, but given that multiple scans have to be stored, and in any orientation, maybe that much storage is needed. One thing we do know is that it’s the biggest fingerprint sensor that we’ve seen so far, coming in at ~39 mm².
Another thing we can say is that the USB, LCD, and camera interfaces are the same as we’ve seen in the A5, A6, and A6X.
More on the fingerprint scanner in another blog; and we’ll undoubtedly be doing a Functional Analysis Report on the A7, so stay tuned.