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ISPSD 2013 pt.2 – Interesting Presentations

contributed by Dr. St.J. Dixon-Warren

The ISPSD 2013 Conference is now in its third day.  Tuesday night the conference banquet was held at the Hotel Nikko Kanazawa. The conference included a dinner speech by Tomotaka Takahashi, founder of Kyoto University‘s ROBO-GARAGE who demonstrated some of his extraordinary robot technology. But the fun and games weren’t limited to the social events – some great semiconductor power technology was on display during the conference sessions.

The Tuesday sessions were focused on Power ICs, Low Voltage Devices, and Packaging, followed by an afternoon poster session. (Note – IEEE conferences tend to frown on picture taking so that the speakers can present interesting things that they may not want in their published documents. Therefore, we have taken a few snappies from the conference proceedings (copyright IEEE) and if you need more information from the papers, you’ll need to visit IEEE-Xplore.)

One presentation of particular interest was given by Lulu Peng of the Hong Kong University of Science and Technology. It concerned novel 3D TSV (through-silicon via) transformer technology for implementation of a digital isolator for gate driver applications.  The device was formed by bumping the transformer die onto the HV circuit die. One of the transformer coils is formed in a layer of BCB dielectric, while the other is formed as trenches in the transformer die surface. TSV’s are used to connect the transformer coils to pads on the backside of the die. The entire stack provides a very efficient form factor. The author presented details of the fabrication process, plus the results of electrical characterization.

Cross sectional view of digital isolator and plan view of transformer

Cross sectional view of digital isolator and plan view of transformer (Source: IEEE/ISPSD)

A second presentation of interest on Tuesday was by M. Yoshino of Mitsubishi Electric Corporation. He presented a 1200 V P-channel MOS structure of level shifting operation in high side/low side driver applications. High side/low side drivers typically feature an electrically floating high side region of the die. Apparently, most applications use N-channel MOS transistors, but there are applications where a P-channel device is preferred, in particular when it is necessary to transmit a signal from the high side to the low side.  The device achieved very low substrate leakage through the use of carefully engineering P-diffusion stripes in the RESURF region between the gate and the drain.

1200V Pch-MOS

1200V Pchannel MOS (plan-view) (Source: IEEE/ISPSD)

Cross-sectional view of a 1200V Pch-MOS

Cross-sectional view of a 1200V Pch-MOS (Source: IEEE/ISPSD)

The conference continued on Wednesday morning with a session on New Materials Power Devices. The “Potential of Diamond Power Devices” was discussed by Yamasaki of AIST. Diamond, as a first row element (carbon), has particularly unique properties, such as high breakdown voltage, high thermal conductivity and high carrier mobility, that make it promising for power applications. Unfortunately, diamond’s donor and acceptor levels are very deep, and hence only a small percentage of the dopants are activated at room temperature. This means that diamond-based devices would have very high on-state resistance, making them unsuitable for conventional power devices such as MOSFETs.  The unique properties of diamond do allow the creation of novel devices that are not possible in Si or Ge.  In particular, the surface of hydrogen-terminated diamond has a negative electron affinity, which allows a diamond PIN diode to serve as an electron emitter in a vacuum switching device.  They fabricated a device and were able to switch 10 kV by application of a 10 V signal to the PIN diode.  They claim that the technology may have applications up to 100 kV for smart grids.

Vacuum switching device. Diamond PIN diode is used as emitter.

Vacuum switching device. Diamond PIN diode is used as emitter. (Source: IEEE/ISPSD)

Time change of IA and VA.

Time change of IA and VA. (Source: IEEE/ISPSD)

The first session ended with a nice presentation by Soogine Chong of the Samsung Advanced Technology Institute. She discussed their new high threshold p-GaN gate (normally-off) GaN HEMT technology. She gave an exceptionally clear survey of GaN HEMT technology in her introduction.  The inclusion of a layer of p-type GaN beneath the gate metal is one of the ways of achieving normally-off operation in GaN HEMT devices. The Samsung devices were made on 200 mm GaN-on-Si wafers and they featured a +2.8 V threshold voltage. They were able to achieve fast on/off switching with rising/falling times of less than 2 ns.  They also tested devices packaged in TO-220 packages which support an average breakdown voltage of 850 V.

Processed p-GaN gate HEMT device with schematic cross-section view

Processed p-GaN gate HEMT device with schematic cross-section view (Source: IEEE/ISPSD)

The final session on Wednesday returned to the topic of Power IC’s, with four talks from major players in the industry, namely NXP, Freescale, STMicroelectronics and IBM.  The first talk from Infineon discussed a clever implementation of a thyristor into NXP’s HV-SOI technology. One of the potential applications is replacing MOS transistors in high-side applications.

Thyristor triggering methods (top) and cross-section of thyristor in HV-SOI

Thyristor triggering methods (top) and cross-section of thyristor in HV-SOI (Source: IEEE/ISPSD)

The second talk was from Freescale and discussed the addition of 110 V N-LDMOS to their 0.13 µm SmartMOS 10 technology.  They claim that the new transistors approach the theoretical silicon limits.

Cross section for conventional NLDMOS

Cross section for conventional N-LDMOS (Source: IEEE/ISPSD)

This talk was followed by one from ST that discussed the addition of 8 V and 42 V transistors to their BCD8 process. The key additional process step was the addition of a thermally grown oxide that was used in the formation of the LDMOS drift region.

8V NMOS (top) and 42V NMOS DR (bottom)

8V NMOS (top) and 42V NMOS DR (bottom) (Source: IEEE/ISPSD)

The final talk was from IBM. The author presented recent results on the addition of 85 V complementary LDMOS devices to their 180 nm power management BCD process.  Special floating plate electrodes were added above the STI in drift region to mitigate the peak electric fields, thus increasing the breakdown voltage.  The specific application will be power of Ethernet (PoE) technology.

Schematic cross-section of floating filed plated PLDMOS (top) and conventional PLDMOS

Schematic cross-section of floating field plated P-LDMOS (top) and conventional P-LDMOS (bottom) (Source: IEEE/ISPSD)

The conference continues Thursday with three more sessions followed by an awards ceremony. Given the decidedly black and white nature of this article, I though it best to leave with a shot from one of the lovely Japanese gardens.