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Plenty of room at the bottom? Intel thinks so!

Contributed by: St.J. Dixon-Warren

The recent 22 nm projects that have gone through our labs  stimulated a revisit of Richard Feynman’s classic paper “There’s Plenty of Room at the Bottom”.  Feynman presented his paper on December 29th, 1959, at the annual meeting of the American Physical Society at the California Institute of Technology (Caltech).

In this paper Feynman gives some early thought to the field of physics that has given rise to advanced microelectronics and to nanotechnology.  He described it as a new “field in which little has been done, but in which an enormous amount can be done in principle.” He pointed out that is “not quite the same as the others {fields of physics} in that it will not tell us much of fundamental physics (in the sense of, “What are the strange particles?”) but it is more like solid-state physics in the sense that it might tell us much of great interest about the strange phenomena that occur in complex situations”.

Furthermore, he argued “that it would have an enormous number of technical applications.”

A few years later, on the subject of scaling, in 1965, Gordon Moore published his seminal paper on the empirical observation that over the history of computing hardware, the number of transistors on integrated circuits has doubled approximately every two years.

Let’s review some of Feynman’s early thoughts on scaling of technological devices to small dimensions with our microscopes on the last few generations of Intel technology.

Putting Encyclopedia Britannica on the Head of Pin

Feynman opens his paper with the question with a topic that probably won’t resonate with anyone born after 1990, “Why cannot we write the entire 24 volumes of the Encyclopaedia Britannica on the head of a pin?” He points on that the head of a pin is about 1/16th of an inch in diameter (1.6 mm diameter or ~2 mm2 area). If we magnify the linear dimensions by a factor of 25,000 then the new area would be the same as all the pages of Encyclopedia Britannica (~1600 m2 area).  Hence, he argued, if we reduce the linear dimensions by a factor of 25,000 then we should be able to print all of Encyclopedia Britannia onto the head of the pin.

Writing Encyclopedia Britannia onto the Head of Pin

Feynman continues with the resolving power of the human eye being 1/120 inch (~210 µm), which is approximately the diameter of the dots in the half tone image in the Encyclopedia. If we scale this dimension down by 25,000 then we would have 8.4 nm diameter dots. Since silicon atoms are 0.22 nm in diameter, this corresponds to ~39 silicon atoms across, and the surface each dot would contain on the order of 1100 atoms (Note, here we depart from Feynman, who considered gold atoms and estimated 32 atoms). Feynman concluded that “there is no question that there is enough room on the head of a pin to put all of the Encyclopaedia Britannica”. It is likely that he felt that manmade feature sizes of 8.4 nm would be near the bottom in terms of technology scaling. In 1959 such features sizes would have seemed a long way off.

The paper continues with the observation that reading such tiny writing would have been quite feasible in 1959 using an electron microscope. He also suggested that duplication was very feasible by stamping the pattern in the plastic (a method in wide use at the time for vinyl LP’s, and coming back into vogue with nano-imprint lithography).  He is less certain, however, as to exactly how to write such tiny text but suggested something that sounds rather a lot like modern e-beam lithography.

In the next section of this article we will review some reverse engineering results for Intel technology, with particular focus on the last ten years. We will compare the feature sizes observed to those proposed in Feynman’s paper.

Sub-100 nm Intel Technology

Chipworks has reverse engineered virtually every generation of Intel technology going back to before 1- µm technology.  During our analysis of Intel’s 45 nm high k metal gate process, my colleague Ray Fontaine posted a review of the Intel reverse engineering results going back to 1992 on the Chipworks blog.

In 2001 we analyzed Intel’s 130 nm process used for the Pentium III. This was the first Intel process to feature copper metal. The contacted gate pitch was 530 nm and the minimum observed metal 1 pitch was 470 nm.  The 70 nm minimum gate length transistors used cobalt silicided source/drain diffusions and cobalt silicided poly gates, with L-shaped sidewall spacers. These dimensions are all more than an order of magnitude larger than the minimum proposed by Feynman.

Intel 130 nm transistors

The 90 nm Intel Pentium 4 Prescott devices were analyzed by Chipworks in 2004.  The 90 nm node saw a number of significant innovations, including nickel silicided source/drains and poly gates, and the introduction of strained transistors using stressed nitride for NMOS and embedded SiGe in the PMOS source drains. The contacted gate pitch was 320 nm and the minimum gate length for the NMOS was 45 nm, corresponding to a shrink by a factor of 0.64 from the 130 nm node. This is slightly better than the 0.7 shrink required by Moore’s Law for doubling the density at each node.

Intel 90 nm PMOS transistors

Intel 90 nm NMOS transistors

Our analysis of the Intel 65 technology in 2006 found essentially a shrink of the dimensions but with no major changes in the materials or the basic technology, other than the use of a nitrided gate oxide.  The contacted gate pitch was 230 nm and the minimum observed gate length was 38 nm.  The contacted gate pitch was shrunk by a factor of 0.72, while the physical gate length was shrunk by only a factor of 0.84.  Achieving the larger shrink in the contacted gate pitch was achieved by shrinking the contacts and the contact to gate spacing by a greater amount.  These dimensions are, of course, very impressive, but they are still significantly larger than the minimum proposed by Feynman in his paper. And we might be slowing down on Moores law.

Intel 65 nm PMOS transistors

Intel 65 nm NMOS transistors

The Intel Xeon E5410 Penryn 45 nm technology, analyzed by Chipworks in 2007, was a major milestone in the development of advanced CMOS technology, since it represented the first commercial high k metal gate technology device.  Early MOSFET transistors were based on aluminum gates; however, polysilicon displaced aluminum in the early 1970’s, due to poly’s ability to form self-aligned gates and due to better matching of the work functions for NMOS and PMOS transistors resulting in lower threshold voltages. The polysilicon gate technology was first developed at Fairchild in 1968, and it became the industry standard for nearly forty years.

The MOS transistors in the Intel 45 nm process features hafnium-based high k (HK) gate dielectric plus complex gate metallurgy that provided a different work function for the NMOS and PMOS transistors. The gates were formed in a “gate last” process by using a sacrificial polysilicon gate which was deposited on top of the HK gate dielectric.  The polysilicon was removed after the transistor engineering was completed and the gates were backfilled with the gate metallurgy (MG). The PMOS used raised SiGe source/drain diffusions, while the NMOS used recessed source/drain diffusions.

The contacted gate pitch for the 45 nm technology was 160 nm, with a minimum observed gate length of 42 nm.  The minimum gate length was actually longer than found in the previous 65 nm generation.

Intel 45 nm PMOS transistors

Intel 45 nm NMOS transistors

Intel’s 32 nm high k metal gate (HKMG) process appeared in the market in 2009. Chipworks analysis of the Intel Core i5 devices found that Intel had significantly evolved the process.  The “gate last” polysilicon replacement process was still used to form the transistors; however, at 32 nm the hafnium-based HK dielectric was deposited after removal for the poly, instead of before deposition. The contacted gate pitch was shrunk by a factor 0.7 to 113 nm with a 30 nm minimum gate length.  Quite dramatic changes were implemented in the contacts, which were formed using very short tungsten stubs, followed by copper via 0s that connected to the copper metal 1.

Intel 32 nm PMOS transistors

Intel 32 nm NMOS transistors

The arrival this year in Chipworks’ lab of Intel 22 nm devices represented yet another major milestone in the development of CMOS technology.   The conventional planar MOS transistor geometry was replaced by a tri-gate geometry, where the transistor gate wraps over a vertical silicon fin structure.

Source: Intel

Planar MOSFET versus finFET Geometry

Chipworks’ Intel 22 nm analysis found the contacted gate pitch to have been reduced to 90 nm, corresponding to a shrink by a factor of 0.8.  The metal gates were broadly similar in structure to those seen at 32 nm, except that the TiAl metal fill was partly replaced by W. The tri-gate fin structure is thinner than the TEM samples, and hence is almost completely obscured by the transistor gate in the conventional contacted-gate cross-sectional direction.

Intel 22 nm PMOS transistors

Intel 22 nm NMOS transistors

The fins are more clearly seen by cross-sectioning in the perpendicular direction, which is across the fins parallel to the transistor gates.  The HKMG wraps up over the transistor fin, which is ~ 8 nm wide at the mid-point.

Intel 22 nm PMOS fin

Intel 22 nm NMOS fin

The scaling of Intel’s CMOS technology has continued to follow Moore’s Law for the past ten years, with the contacted gate pitch scaling as approximately 4X the technology node. Each node corresponds to a shrink by a factor of 0.7, which corresponds to a doubling of the density of transistors per unit area.  The gate length has been scaled more slowly, while the gate oxide for poly processes leveled out at ~1.5 nm.   Intel is apparently gearing up to make 14 nm technology, and we can expect a contacted gate pitch of about 60 nm; however, scaling the contacted gate pitch may not require that they scale the dimensions of the transistor fins.

The transistor fins found in the Intel 22 nm devices have essentially the same physical width as the minimum feature size proposed by Feynman in his 1959 paper.  The minimum fin pitch in the Intel 22 nm process is 60 nm; however, one could argue that Intel should now be nearly capable of printing the entire contents of Encyclopedia Britannica on to a die that is the size of the head of a pin – in fact, they claim that > 100 million 22-nm transistors will fit.

Source: Intel

Feynman would almost certainly be impressed by this technical achievement, and he’d likely agree that there is no longer plenty of room at the bottom, at least for 2D planar microelectronic device layout. But his visionary paper isn’t done.  Feynman’s paper includes a discussion of the extraordinary information densities possible in 3D structures.  He points out “that all of the information that man has carefully accumulated in all the books in the world can be written in the form of a cube of material one two-hundredths of an inch wide;” however, even though the tri-gate structure is the first and simplest excursion into 3D devices, fabricating high density 3D devices continues to be essentially unfeasible.

This doesn’t appear to be slowing Intel down – their R&D pipeline is heading down to 5-nm devices, though what they will look like is still to be decided.  There’s a few more interesting years (or decades) to come in nanotechnology!

Source: Intel

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Chipworks completed a comprehensive analysis of the Intel 22 nm technology in early 2012. Our analysis included detailed structural analysis of the technology, as well as electrical measurements of the MOS transistors in the SRAM, analysis of the packaging technology and analysis of the die layout.  Some of the material in this article will be presented by our own Dick James’ at the 2012 Custom Integrated Circuits Conference where he is presenting the latest analysis of Intel technology.