Contributed By: Rajesh Krishnamurthy
The increasing demand for high frequency operation, high performance, high I/O density, and smaller form factor chips for smart phones, tablets, and other mobile handheld products is creating serious challenges for those companies that design, manufacture, and package those devices.
Apart from increasing the processor speed by the scaling of transistors, there is a constant need for smaller and fewer chips on the main board of the device, and for increased speed/bandwidth between processor, memory, and logic ASIC chips. Many schemes of integrating the processor chip with memory and logic ASICs in a single package have been attempted. One such scheme is to combine flip-chip and wire bond interconnections in a single package, referred to as flip-chip package-in-package (fcPIP) as proposed by STATSChipPAC. The fcPIP package belongs to a class of 3D packages that vertically stack a pre-tested chip, such as memory, in a land grid array (LGA) format, also known as internal stacked module (ISM), and bare chips into one flip-chip ball grid array (FBGA) package assembly.
Chipworks recently analyzed packages from the Qualcomm Snapdragon processor family, namely the MSM8660 with dual 1.5 GHz Scorpion processors and the QSD8650 with a single 1 GHz processor. Figures 1 and 2 are top and bottom view photographs of the MSM8660 and QSD650 packages, respectively. Qualcomm refers to the MSM8660 package as an NSP package, (Nanoscale package), with 976 solder balls formed on the back of the 14 mm x 14 mm x 1.3 mm thick package (including solder balls). The solder balls are placed with a minimum pitch of 0.4 mm. It is probable that Qualcomm describes all of its FBGA packages with 0.4 mm pitch solder balls as NSP. The QSD8650 package, on the other hand, has 604 solder balls formed on the back of the 15 mm x 15 mm x 1.4 mm thick package (including solder balls), which is almost the same size package as the MSM8660. The solder balls for the QSD8650, however, are placed at a 0.5 mm pitch.
Plan-view X-ray photographs of the MSM8660 and QSD8650 packages with solder balls are shown in Figure 3. Close examination shows that the MSM8660 contains one flip-chip and one wire bonded die, and the QSD8650 has two flip-chip and one wire bonded die.
Figure 4 is a side-view X-ray, and Figures 5 and 6 are optical cross section photographs, respectively, of the MSM8660 package. The MSM8660 assembly consists of a larger Qualcomm SoC die flip-chip bonded to a first printed wiring board (PWB 1) at the bottom of the package, and a second die wire bonded within a smaller ISM package, stacked over the bare SoC die and itself wire bonded to the main PWB (PWB 1). The embedded upper package contains a Samsung LP DDR2 SDRAM die wire bonded to the second PWB (PWB 2). Looking closely at the left image of Figure 6, we can see that the SDRAM was encapsulated before being flipped and laid on top of the SoC, before wire bonding the subassembly to the main substrate PWB1. There are also two passive elements bonded to the bottom PWB 1 and embedded within the package material.
Figure 7 shows side-view X-ray images along the length and width of the QSD8650 package. The QSD8650 is also an fcPIP type package with two bare dies, an SoC and a DSP, flip-chip bonded to the PWB 1, and an SDRAM chip wire bonded to an upper PWB2 board, itself wire bonded to the PWB 1.
When comparing the packaging used for the 1.5 GHz MSM8660 and 1 GHz QSD8650, which represent two generations of processors manufactured with two generations of logic processors (45 nm and 65 nm, respectively), it is worthwhile noting that both processors are packaged with almost identical sized fcPIP type packages. The SoC processor die used for the two processors are almost identical in size. The MSM8660 processor package, however, has integrated a 512 Mbit DDR2 SDRAM chip with the SoC processor die, while the QSD8650 has incorporated a DSP chip in addition to a slower 512 Mbit DDR SDRAM chip, along with the processor SoC die.
Analysis and reports on devices discussed in this blog