Contributed by: Sinjin Dixon-Warren
The Apple A7 processor used inside the iPhone 5s represents an extraordinary piece of engineering. Some details, such as the die layout, were discussed in an earlier blog. The A7 is fabricated with Samsung’s 28 nm low power (LP) gate first, high-k metal gate (HKMG) process technology. The process features nine layers of copper metallization with low-k dielectrics, plus an additional top aluminum metal layer. This blog article will focus on the front end of line (FEOL) transistor structure used in the A7, with comparison to advanced technologies used by both Apple and other vendors. The A7 gate first transistor structure is based on the Common Platform Technology, which is an alliance of IBM, Samsung, and GLOBALFOUNDRIES.
Chipworks has analyzed several generations of the Samsung process used to fabricate the A-series processors used in the iPhone and other Apple products. The A4 processor, released in September 2010, used a Samsung 45 nm polysilicon transistor process technology with 180 nm contacted gate pitch. The NMOS and PMOS transistor structure was essentially identical, with the main observable differences being in the materials used for the polysilicon gate and source/drain silicides.
Apple moved to a 10 metal, 32 nm HKMG process when they launched the A5 processor in March 2011. The gate first transistors featured a 130 nm contacted gate pitch, with a SiGe channel for the PMOS transistors, and separate work function metals for the NMOS and PMOS transistors. The SiGe channel improves the PMOS hole mobility and serves as part of the transistor work function engineering. The A6 processor, launched in September 2012, was also built with the Samsung 32 nm HKMG process.
The A7 is Apple’s first 28 nm device. The process technology is broadly similar to that used at 32 nm, with an ~10% shrink of the contacted gate pitch to 120 nm. The PMOS and NMOS transistors are easily distinguished due to marked differences in the transistor structure.
The NMOS transistors feature an NMOS work function metal gate (MG) deposited onto the high-k (HK) gate dielectric, which is comprised of hafnium oxide deposited over a thin layer of silicon dioxide. The process is described as gate first since the silicided polysilicon gate is deposited after the HKMG gate stack has been formed.
The main distinguishing features of the PMOS transistors are the presence of a SiGe channel beneath the PMOS gates and a separate PMOS work function metal deposited over the HK dielectric stack. The NMOS MG layer is present over the PMOS MG layer, indicating that the PMOS transistors were formed first in the process flow. This NMOS MG layer would have no effect on the electrical characteristics of the PMOS transistor, although it may serve as a barrier to protect the PMOS MG layer during the polysilicon deposition process step. There are minor differences in the shape of the sidewall spacer structure (SWS) for the PMOS as compared to the NMOS transistors, while both transistor types are sealed with the same contact etch stop layer (CESL).
The requirement for two different metal gates, with different work functions, is one of the major challenges for HKMG process technology. It is quite easily achieved in polysilicon gate technology through doping of the gate polysilicon as N-type for the NMOS and P-type for the PMOS transistors. A review of work function engineering has recently been published. Variations on the gate first PMOS SiGe channel technology used for the A7 have been used by GLOBALFOUNDRIES in the AMD 32 nm devices, and by IBM in the Power 7+ processors.
By contrast, Intel and TSMC have avoided the use of SiGe in the PMOS channel region; they achieve the work function difference purely through engineering of the metal gates. Furthermore, Intel and TSMC used a gate replacement (gate last) process, where the transistor engineering is completed using conventional polysilicon gates. The polysilicon is then removed and replaced with the NMOS and PMOS HKMG gate stack. A discussion of TSMC 28 nm process technology, which comes in four flavors, can be found in a previous blog posting. A review of many generations of Intel technology can be found in another earlier blog posting.
Related Chipworks Reports:
- Apple A4 APL0398 Microprocessor Extracted from the iPad and iPhone 4 (APL0398B01 Die Markings) Samsung 45 nm Low Power CMOS Process, Process Analysis (PPR-1012-90)
- Apple A5 APL2498 Samsung 32 nm Gate First HKMG CMOS Process Structural Analysis (SAR-1204-801)
- Apple A6 APL0598 (APL0589B01 Die Markings) Application Processor Extracted from the iPhone 5 Basic Functional Analysis (FAR-1209-801)
- Apple APL0698 A7 Applications Processor Samsung 28 nm HKMG CMOS Process Review (PPR-1310-801)
- Altera 5SGXEA7K2F40C2ES Stratix® V TSMC 28 nm HP Gate Last HKMG CMOS Process, Process Review FEOL Analysis (PPR-1109-801)
- AMD A8-3800 Llano GLOBALFOUNDRIES 32 nm Gate First HKMG Silicon-on-Insulator (SOI) CMOS Process Structural Analysis (SAR-1107-801)
- IBM POWER7+ Server 52Y9243 32 nm Dual Stress Liner SOI CMOS Process with eDRAM Structural Analysis (SAR-1309-201)
- Intel Q3GM ES 32 nm CPU (from Core i5 660) Structural Analysis (SAR-0910-801)