Contributed by: Anton Riley(Multiprobe) and St.J. Dixon-Warren (Chipworks)
The Fabless semiconductor model is extremely popular but competition between the foundries can be fierce. The choice of foundry takes into account factors such as cost, projected yield, performance, etc. Qualcomm, a giant foundry customer, had their 28nm Low Power “SHELBY” die dual sourced from both Samsung and TSMC. The SHELBY is the primary die in the MDM9215 4G/LTE “Gobi” modem used in several smartphones. From a performance standpoint, these two die should theoretically be identical.
This represents a unique case of leading technology, available to the public, produced by two predominate foundries just waiting for a head-to-head performance comparison. Chipworks the recognized leader in reverse engineering and Multiprobe the designers of the worlds most advanced nano-electrical characterization tool partnered together to measure the performance of the dual sourced chip.
Chipworks acquired the HG11-N3877 fabricated by TSMC and the HG11-N9204 fabricated by Samsung from a variety of smart phones. The die were de-processed by Chipworks to contact level to measure the effective gate width, layout and cell density. Several TEM cross sections were performed by Chipworks to record the gate lengths for nominal NMOS and PMOS transistors in the SRAM array for each foundry. The widths were used by Multiprobe to normalize the currents for the measured transistors.
Several SRAM cells from both foundaries were qualified electrically using the atomic force prober (AFP) by Multiprobe against eleven performance parameters. The transfer characteristics (ID vs VGS) were used to measure the transconductance (gm), linear and saturation threshold voltages (VT, lin VT,sat), on-state drive current (ION) and off- state leakage currents (IOFF) for the NMOS and the PMOS transistors. The output characteristics (ID vs VD) were used to measure the transistor on-state resistance (RON), and the Channel length modulation parameter λ for VGS @ 1 V. For all measurements an average value and standard deviation was calculated to qualify the performance consistency.
In a perfect process, there would be no detectable variation over the memory cell transistors, however, perfect is hard to achieve. The AFP’s PicoCurrent imaging mode was used to survey large blocks of the SRAM. The block below contains about 3500 individual device contacts. PicoCurrent microscopy is a continuous image map of the surface locating subtle or gross variations in current flowing between the imaging probe tip and the grounded chuck or adjacent probe. Using this technique several systematic variations were identified on both parts contributing to large standard deviations in the transistor measurements. The variations are caused by the device properties under the metal contacts.
Four probe measurements were performed on several of these anomalies measuring the Transfer and Output Characteristics of the devices involved. For each of these targeted anomalies a consistent shift in the voltage threshold was measured. Different systematic anomalies were present on the part from Samsung and TSMC. The final results will be published in the International Symposium of Failure Analysis (ISTFA) 2013. Included in the publication are the complete set of electrical comparative data, SEM and TEM Physical inspection images.