contributed by Ray Fontaine
The International Image Sensors Workshop (IISW 2011) is recognized as the premier event in digital imaging. Companies share the pixel performance gains realized by innovative process development, sophisticated circuit designs, and new manufacturing techniques. Contrasting other conferences where only robust completed work or selected results are shared, at IISW there is a spirit of sharing work in progress. Nearly the entire community is represented on the world’s stage, and at times a think tank atmosphere emerges with many ideas freely shared along with visions of the future in what is a young and growing field.
Chipworks’ role at IISW was to review the state-of-the-art of small pixel CMOS image sensor (CIS) devices in production. Currently, the CIS community is transitioning from the 1.4 µm to 1.1 µm pixel generation of the small pixel roadmap. Several trends are evident in small pixel development as can be learned in the Chipworks paper (Paper IISW 1.4um Pixel Generation) and presentation. In summary, it seems that nearly all of the small pixel leaders have moved to advanced technology generation production using 300 mm wafers. Of the eight 1.4 µm devices reviewed, all were fabricated using either 90 nm or 65 nm processes. Moving forward, Panasonic recently announced CIS production using hybrid 45/32 nm design rules as a way to extend its front illuminated (FI) pixel process. The roadmap for back illuminated (BI) pixel manufacturing includes OmniVision and TSMC who are developing 40 nm process technology for their future small pixel generations.
Quickly reviewing the status of small pixel development, we heard from Aptina who were able to execute the 1.4 µm generation using the FI approach. Their A-pix process, which employs deep photodiodes and light pipes, was able to match the performance of their 1.4 µm BI process. By deferring the cost of BI insertion into its small pixel roadmap by a generation, Aptina has remained competitive while developing BI for future generations. Aptina is also boosting the performance of its previous pixel generations by inserting newly developed process modules into, for example, 5.6 µm pixel devices for automotive applications.
STMicroelectronics introduced us to its deep trench pixel isolation (DTI) technology, recently discovered in the 3 Mp and 5 Mp CIS camera modules of the RIM Blackberry Tablet. Borrowed from trench capacitor DRAM manufacturing, the big hurdle with this approach is to passivate the surface states created by the increased Si/SiO2 interfaces. STMicroelectronics showed that its passivation implant process effectively reduced the average dark current in line with its conventional process. We also learned that the DTI process module will be inserted into STMicroelectronics’ upcoming BI process flow.
Samsung continues its emergence in the silicon imaging space and discussed its FI processes with and without light pipes, and also its BI processes. Chipworks has detailed the Samsung BI process fabricated on 200 mm wafers, and Samsung announced at the conference that it will move to 300 mm wafers for future BI production.
OmniVision and fabrication partners TSMC discussed the transition to 65 nm design rules for OmniBSI2 production using 300 mm wafers. The topics in the OmniVision paper that caught my eye were the 40 nm design rules and the possible migration to hole detectors and RGB + clear color filter array (CFA) sub-micron pixels. This may be an interesting insight into OmniVision’s strategy, possibly explaining its recent acquisition of the Kodak patent portfolio. Kodak has previously demonstrated hole detectors in its 2008 ISSCC paper, and RGB + W CFA in its 2009 IISW paper.
Speaking of awards, Sony had the distinct honor of collecting this year’s Walter Kosonocky award for its 2010 ISSCC paper detailing its high-speed BI device. This device and technology have been a huge win for Sony, capturing sockets in Casio, Canon, and of course Sony digital still cameras (DSC).
The breadth and depth of the biennial IISW 2011 cannot be conveyed in a blog posting, so I’ll leave it at that for now. On behalf of my fellow attendees, I would like to once again thank the conference organizers for managing through the difficulty of the natural disaster in Japan. While 2011 marked the 25th anniversary of the IISW, the workshop content as a whole demonstrated how truly young the digital imaging sector is and how very many avenues there are left to pursue.
1.4 µm CIS Generation Reports by Chipworks
Aptina MT9P111 5 Megapixel, 1/4 Inch Optical Format, System-on-Chip (SoC) CMOS Image Sensor
OmniVision OV5642 1.4 µm Pixel Size Back Side Illuminated (BSI) 5 Megapixel CMOS Image Sensor
Samsung S5K3H1GX 1/3.2 Inch Optical Format 8 Mp, 1.4 µm Pixel Size CMOS Image Sensor
Sony IMX046 8.11 Megapixel, 1.4 µm Pixel 1/3.2” Optical Format CMOS Image Sensor
STMicroelectronics 5 Mp, 1.4 µm Pixel Pitch CMOS Image Sensor (5953BA Die Markings)
Toshiba 16 Mp, 1.4 µm Pixel Pitch CMOS Image Sensor from FujiFilm F550EXR (HEW4 Die Markings)
