Chipworks

Contributed by James Mihaychuk. 

While at the sold-out International Image Sensors Workshop (IISW) in Japan, our image sensor analyst, Ray Fontaine, presented a retrospective on the 1.4 µm pixel generation of front illuminated (FI) and back illuminated (BSI) CMOS image sensors (CIS). The presentation highlighted the leaps forward in semiconductor process sophistication that has enabled improved performance and lower cost for the millions of multi-megapixel image sensors found in our smartphones and digital still cameras (DSCs). 

Despite being a retrospective, the innovation in this generation continues apace. A recent and very interesting chapter in that ongoing story describes the inner workings of the 16 megapixel Toshiba HEW4 BSI CIS found inside the new Fujifilm F550 EXR camera (Figure 2). The F550 is packed with features that enhance picture quality and user experience. These include image stabilization, HDMI video out, anti-blur, fast auto focus, intelligent flash, GPS, fast upload of tagged images, panoramic shots, face finder, face recognition . . . and yes, even dog and cat recognition! 

Figure 2. Fujifilm FinePix F550 EXR

All of this functionality was enabled through technology from a variety of chip vendors. The key design wins for the F550 includ the following devices.

Figure 3. Toshiba HEW4 image sensor assembly – front and back

The BSI image sensor architecture uses the Fujifilm EXR system of paired diagonally arrayed pixels, previously found in CCDs (Figure 4). The microlens array and color filter array are completely free of opaque metal structures, achieving 100% fill factor. The CSCM package markings indicate Toshiba as the maker and China as the country of manufacture. The “Made in China” markings suggest that the camera module assembly may have been through the joint venture between Jiangsu Changjiang Electronics Technology and Toshiba Semiconductor (Wuxi). 

Figure 4. HEW4 active pixel array center

The HEW4 chip itself was fabricated using the Toshiba Oita 300 mm wafer line, using a 65 nm logic process adapted to BSI image sensor production. Toshiba announced this process in 2009 through an IISW conference paper and press release. Many details of the device architecture are similar to other Toshiba Dynastron™ CIS chips. This design win with Fujifilm reinforces Toshiba’s stated position as number 4 worldwide in CIS sales and “Leader ‘Behind the Scenes’ in Image Sensors.” 

The most telling aspect of how the HEW4 BSI chip gets integrated into a chip scale camera module involves the use of very high density arrays of polysilicon filled through silicon vias (TSVs), to form the electrical interconnect between the back side wire bonds and the CMOS integrated circuits on the front of the wafer (Figure 5). These are the first true submicron TSVs that Chipworks has seen deployed in volume production. 

Figure 5. HEW4 TSVs – SEM detailed view

Getting back to BSI image sensors, a variety of approaches to the front-to-back interconnect have been deployed in recent years. Perhaps the simplest approaches are those that use bond pad openings that extend all the way through the thin substrate to connect directly to the front side metal layers. In addition, several IDMs use some form of low density “hole based” TSV method. Rather than alter their chip design and process flow, some companies turn to wafer level chip scale packages instead of TSVs. Depending on the volume of devices required, these chip makers would either buy packaging services or license technology to have access to interconnects that wrap around the edge of the die. 

In this context, the HEW4 device defines a new category of CIS camera module with its closely packed, poly-filled submicron TSVs that connect the back side aluminum bond pads to the front side copper lines. This technology is non-trivial to implement. Once mastered and with appropriate economies of scale in play, however, this advanced TSV process saves valuable silicon area and can reduce the size of the camera module. 

Toshiba’s System LSI business has undergone restructuring recently, including an end to the joint venture with Sony at Nagasaki Semiconductor Corporation (NSM). Toshiba CEO Norio Sasaki has put forth an ambitious long term plan to grow Toshiba into a true multinational serving the areas of digital products, electronic devices, social infrastructure, and home appliances. Having learned to navigate rough seas, this skilled mariner now wants to leverage 300 mm mass production of BSI sensors to achieve 30% market share by 2013! 

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We are just wrapping up our analysis of Sony’s latest CIS, the IMX081. This is the first 1.1 µm pixel device commercially available, and is just chock full of interesting features.

Camera module from SE Cyber-shot S006 that contains the IMX081

Built on a 90 nm design rule process, Sony has implemented a new pixel layout and schematic architecture, moving to an eight-shared pixel architecture (1.375T per pixel effective), compared to the two and four-shared pixel architectures that have been common for the last few years in small pixel size sensors. In addition, advanced packaging features are used with both active and passive embedded devices found in the package.

There is a lot of information for our customers’ competitive analysis teams to analyze when they review the report.

What makes the part interesting for us is our finding that, with the 1.1 µm BSI generation, Sony has migrated to using bulk silicon substrates instead of SOI. The previous Sony BSI sensors we have analyzed (the IMX061 and IMX050) have been fabricated using an SOI starting wafer. This is a more costly substrate, but likely an easier process to implement.  By having both processes available, we can presume that Sony was able to identify the yield limiting contributions from the bulk polishing process, and fine tune the yield to achieve a high yielding and very cost effective process.

How do we know that Sony has moved to bulk substrate? That is an interesting question, and one where the review of the forensic evidence gives insight into the art of reverse engineering. Indeed, at the start of our analysis, we were unsure if we would be able to identify the use of SOI or bulk substrate starting wafer – it is not as if this is labeled on the die for us. Also, during fabrication over 90% of the starting material is removed for both processes, leaving us looking for circumstantial indicators.

So here is the image (the smoking gun) that provides the evidence that Sony has indeed adopted a bulk Si process.

Bottom (light side) of a deep trench isolation in the IMX081

This is a deep trench that goes through the whole sensor. We are imaging the bottom (light side) of the trench here, with a metal and dielectric film at the interface. What we can see is the material that fills the trench has a seem running down the middle; this seam extends to the very bottom of the trench. Thus, we can infer that to achieve this, the bottom of the trench has been polished back along with the silicon substrate prior to the dielectric and metal depositions. For an SOI process, the trench bottom would align with the oxide interface, thus the seam from the trench fill material would not extend to the bottom.

Overall, this is  a rather elegant piece of reverse engineering from the Chipworks analysis team.

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This afternoon I paid a visit to the FujiFilm booth and inquired about their new BSI EXR CMOS Image Sensor. I was introduced to Mr. Shizuo (Ben) Habuta san, Director of Product Development for FujiFilm’s Electronic Imaging Products Division. Ben was kind enough to take some time to talk to me about this new BSI sensor.

At Chipworks we have analyzed many Fujifilm sensors and they have traditionally employed CCD sensors. So you can imagine our surprise when Fujifilm announced a BSI CMOS Image Sensor.

To date, Chipworks has only seen BSI sensors from Sony, Omnivision and Samsung. So now fourth out of the gate (seen by us) is FujiFilm.

The new BSI EXR CMOS Image Sensor is a 16Mp, ½ inch format device. This sensor is being used in three new cameras from FujiFilm; The Finepix F500 point and shoot ($329), the Finepix F550 point and shoot with built in GPS ($349) (all the rage here at CES) and the DSLR-like (to quote Ben) HS20 ($499). At these price points they are targeted at those interested in higher end imaging and will be in camera stores throughout North America in March. A point-and-shoot that is not destined for Best Buy?  Well, we were told that mass electronics retailers won’t even look at stocking a point and shoot on their shelves unless the price is in the sub – $200 range.

Ben stated that the BSI EXR was designed and manufactured by FujiFilm but unfortunately did not share details on the process node or pixel size. Speculation by commentators on Image Sensors World blog guess it is a 1.4 µm pixel. I guess we will have to wait until March to get one of these sensors into the lab so we can measure pixel pitch and review and understand the transistor layout. Oh well!

Ben tells me that the secret behind this BSI sensor is not just that it is BSI, he tells me its success is a result of a merge of the color filter technology from their great CCD’s  and the new BSI design.  The graphic below shows a diagonal filter and photodiode layout, something that has been in all the FujiFilm CCD cameras we’ve seen.

I asked Ben if FujiFilm had any intention of selling this sensor on the open market for other camera companies and he told me that FujiFilm developed this sensor for their own cameras and no one else. They have no intention of selling it on the open market and trying to compete with giants like Sony or Omnivision. Given the price of these cameras compared to other point and shoots I guess FujiFilm intends to make back their investment through sales of their own cameras. Sounds to me like they need to sell a lot of cameras given what we know about the development efforts and time to develop a BSI process.

Reflecting back for a moment, I find it odd that it appears that FujiFilm has beaten manufacturers like STMicroelectronics and Toshiba to the street with a BSI sensor. I can loosely equate this to Panasonic and how they got their 65 nm-and 45-nm CMOS processes simultaneously with Intel, and beating all other IDMS to market, and Panasonic did it for their own products as well. Well, I am sure the product development teams at FujiFilm did their return on investment analysis before they spun any photo resist. I wish them great success and I cannot wait to get one of these cameras in March and play with it and then get down to the heart of the matter, the BSI process and layout.

Viva Las Vegas!

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by Ray Fontaine, Image Sensor Analyst

I mentioned in a previous blog that image sensor companies would be deploying BSI technology when their targeted applications demanded it. Admittedly, I was mostly thinking about mobile phone applications where form factor and ever shrinking pixel pitch seems to be the primary driver for BSI.

As noted in several news articles, nicely consolidated in Image Sensors World blog postings, BSI is also making headway in digital still camera (DSC) and video camera applications. The latest Sony BSI design win that we’ve seen is from Casio’s EX-FH100 EXILIM DSC. In fact we documented a number of interesting and innovative devices in a product teardown on this camera.

This product is positioned as a high speed EXILIM camera with a wide-angle 24 mm, 10x optical zoom lens. It offers a maximum burst rate of 40 fps for still images (maximum image size of 9.0 Mp, maximum capacity of 30 frames), and also a 1,000 fps high-speed movie mode for slow motion movie functionality.

The image signal processor (ISP) is a Sony CXD4122GG 2^nd generation camera system chip designed for use with Sony Exmor R CMOS image sensors (CIS). The CXD4122 is capable of high-speed imaging of up to 10 Mp images at 50 fps, and high-speed video at 240 ‘ 1,000 fps.

Sony CX412D2GG Image Sensor processor

Before getting into the CIS silicon, it is worth noting that Sony’s IMX050 BSI sensor displays quite a lot of innovation at the packaging level. We’ve previously seen the Sony BSI die elsewhere, but this is the first time we’ve seen it packaged with embedded passive components in the chip carrier. Sony claims the new miniaturized package is 30% smaller than their existing solution. A detailed process report is underway to study the packaging.

Planar and Side X-Ray of Sony IMX050 CIS ‘ Embedded Passives

The IMX050 is a 1/2.3′ optical format, 1.65 ‘m pixel pitch CIS featuring Sony’s 2^nd generation BSI process technology and column-parallel A/D conversion design. Sony’s Exmor-R backgrounder describes the inadequacies of CCD’s for this application as being the driver for their high-speed CIS development. The implementation of BSI also resulted in an approximate 2x increase in sensitivity as compared to an equivalent front-illuminated pixel.

Sony presented their high-speed BSI technology in February at the 2010 International Solid-State Circuits Conference (ISSCC). Our preliminary findings indicate the CIS from the ISSCC presentation is a match to the Casio sensor. Essentially, the new Sony technology hits across three industry/consumer sweet spots: high-speed readout, high resolution, and high signal-to-noise (SNR). A full imager process review (IPR) report will provide coverage of the high-speed BSI pixels and 0.14 ‘m copper fabrication process.

Sony IMX050 CIS ‘ 2010 ISSCC Paper 22.9 (l), Chipworks Back-of-Die Photo

In summary, Sony have a very definite strategy to service high-performance, high value consumer CIS applications. As low resolution, small pixel mobile sensors have become a commodity, Sony has chosen to play at the other end of the spectrum where technical innovation is likely to derive higher margins. As seen in this teardown example, they are also able to grow their business by winning designs for their technology in their consumer electronics competitors. One final observation is the continued displacement of CCD’s in high-end DSC’s, as we’ve already seen in some Canon and Sony point and shoot cameras.

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Click here for a list of reports related to the Casio Exilim.

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