We recently acquired Samsung’s latest DDR3 SDRAM, with package markings K4B2G0846D-HCH9. This part number lines up with a press release from Samsung last year about their 2 Gb 3x-nm generation DRAMs. The first thing we did was measure the die size. This chip is 35 sq mm, compared to the previous generation 48 nm Samsung 1Gb DDR3 SDRAM, which is 28.6 sq mm. Clearly this 2 Gb die is much smaller than 2X the 48 nm 1 Gb die, so our assumption that we have a 3x nm part looks good so far.
Figure 1: Samsung 3x DDR3 SDRAM Die Photo
Next we did a bevel-section of the part to take a look at the cell array. We were surprised with what we found. The capacitors are laid out in a square array instead of the more usual hexagonal pattern (see below), and the wordline (WL) and bitline (BL) pitches are both about 96 nm. The usual method of determining DRAM node is to take half the minimum WL or BL pitch. That places this DRAM at the 48 nm process node, the same as the previous Samsung generation (at 48 nm). So why does the die size look like it should be a smaller technology? The answer lies in the cell.
Figure 2: Plan-View TEM Image of Capacitors
For those who don’t design DRAM, a short primer is in order.
DRAM uses a convention of describing cell size in terms of the minimum feature size, F. Historically DRAM cells used an 8F2 architecture. A diagram of an 8F2 cell is shown in Figure 3. This diagram shows that cells are only placed at ½ the locations where BLs and WLs cross. This allows for the use of a folded bitline architecture. This architecture uses a reference bitline that is adjacent to the read bitline. This helps eliminate noise, since most noise will be common mode. In order to decrease cell area companies came out with the first 6F2 cells in 2007. This 6F2 architecture is now used by all major players in the DRAM market. Figure 4 shows the layout of this cell. Since more than half the possible cell locations are now filled, folded bitline is no longer possible. Hence all companies have now moved to an open bitline architecture, despite inherent noise issues (which we will not get into at this time). In a 6F2 architecture two-thirds of the WL/BL intersections are filled with storage cells.
Figure 3: 8F² architecture
Figure 4: 6F² architecture
Source: Nikkei Electronics Asia, January 2008
A 4F2 architecture is defined as having a memory cell at each and every possible location, that being each and every crossing of WL and BL. The simplified layout architecture would be the same as the 6F2 architecture above, but with the cell being 2F X 2F.
Back to the device in question.
The first piece of evidence
The 48 nm SDRAM has a cell size of 0.014 sq µm and this new SDRAM has a cell size of about 0.0092 sq µm. If we take the half-WL pitch as the minimum feature size (F), we get an F of 48 nm for this process. The cell area of 0.0092 sq µm is exactly 4 x F squared, or 4F2. Is this the world’s first 4F2 cell? From this point of view it certainly appears so. The cell is four times the size of the minimum feature, squared.
Figure 5: DRAM Roadmap Source: Nikkei Techon
The second piece of evidence
If a 4F2 architecture is defined as having a memory cell at each and every possible location, and what we see on this Samsung DRAM seems to do exactly that, then maybe we are looking at the first 4F² architecture. Let’s look just a bit closer to be sure.
The smoking gun
We compared the poly and active layout under the array between the 48 nm SDRAM and this new one. The images below show that they both have very similar layouts. The angle of the active silicon (diffusion) direction is about the same. The active areas are ovals. Each diffusion has two wordlines crossing it. There is a gap in all the active stripes, such that a third WL does not cross active on this diagonal active stripe.
Figure 6: Samsung K4B1G0846F 48 nm 1 Gb DDR3 SDRAm, Poly and Active Area Image under Cell Array
Samsung K4B2G0846D 2 Gb DDR3 SDRAM, Poly Remnants and Active Areas under Cell Array
This new DRAM therefore has a very similar cell layout to the previous one. In both cases the wordlines do not have a transistor under them at every possible location that a transistor would fit. Rather, one of every three possible transistor locations is filled with a break in the diffusion stripe. In our opinion this is a critical factor in identifying a 6F² cell, that in a 6F² architecture 2/3 of the WL/BL intersections are filled with storage cells. As we noted above, a 4F² cell really should have transistors at every possible transistor location. When we look at the pitch of the diffusions in this new DRAM, we see it is much tighter. In fact, along the WL direction the diffusion pitch is now 64 nm, whereas in the 48 nm SDRAM this pitch was 96 nm. So if you take half the minimum pitch in the chip as the node, this is a 32-nm part (ITRS 2009 still defines F as half the contacted M1 pitch, which would be 48 nm).
Conclusion
So, do we have a 32 nm node, and a 6F² architecture? Maybe. The only issue is that if we use 32 nm as F, then when we plug that into the 6F² equation we get 0.0061 um² as the cell size. However, the cell size is actually 0.0092 um². If we use that number and use the equation to calculate F we find that F=39nm. So… do we call this a 32 nm or a 39 nm node? It depends how you calculate it – either way it’s a 3x! So, although it’s a little disappointing that I don’t think we can announce the worlds first 4F² DRAM, we can announce the worlds smallest node, 32 or 39 nm, production 6F² DRAM. Samsung have had to put in a few process tweaks to squeeze the cells into the much smaller area, mostly at the transistor and STI level. We’re still looking at it, so we may not have the whole story yet, but some of what we’ve seen so far is:
• Ti-? (likely TiN)-gate buried wordline transistors
• STI filled with nitride in the array
• Bitlines at the same level as peripheral transistors.
See available Circuit Analysis and Process Analysis Reports on the Samsung K4B2G0846D-HCH9.
