Chipworks

Contributed By: Rajesh Krishnamurthy

The increasing demand for high frequency operation, high performance, high I/O density, and smaller form factor chips for smart phones, tablets, and other mobile handheld products is creating serious challenges for those companies that design, manufacture, and package those devices.

Apart from increasing the processor speed by the scaling of transistors, there is a constant need for smaller and fewer chips on the main board of the device, and for increased speed/bandwidth between processor, memory, and logic ASIC chips. Many schemes of integrating the processor chip with memory and logic ASICs in a single package have been attempted. One such scheme is to combine flip-chip and wire bond interconnections in a single package, referred to as flip-chip package-in-package (fcPIP) as proposed by STATSChipPAC. The fcPIP package belongs to a class of 3D packages that vertically stack a pre-tested chip, such as memory, in a land grid array (LGA) format, also known as internal stacked module (ISM), and bare chips into one flip-chip ball grid array (FBGA) package assembly.

Chipworks recently analyzed packages from the Qualcomm Snapdragon processor family, namely the MSM8660 with dual 1.5 GHz Scorpion processors and the QSD8650 with a single 1 GHz processor. Figures 1 and 2 are top and bottom view photographs of the MSM8660 and QSD650 packages, respectively. Qualcomm refers to the MSM8660 package as an NSP package, (Nanoscale package), with 976 solder balls formed on the back of the 14 mm x 14 mm x 1.3 mm thick package (including solder balls). The solder balls are placed with a minimum pitch of 0.4 mm. It is probable that Qualcomm describes all of its FBGA packages with 0.4 mm pitch solder balls as NSP. The QSD8650 package, on the other hand, has 604 solder balls formed on the back of the 15 mm x 15 mm x 1.4 mm thick package (including solder balls), which is almost the same size package as the MSM8660. The solder balls for the QSD8650, however, are placed at a 0.5 mm pitch.

Figure 1 Qualcomm MSM8660 and QSD8650 Snapdragon Processor Top Package Views

Figure 2 Qualcomm MSM8660 and QSD8650 Snapdragon Processor Bottom Package Views

Plan-view X-ray photographs of the MSM8660 and QSD8650 packages with solder balls are shown in Figure 3. Close examination shows that the MSM8660 contains one flip-chip and one wire bonded die, and the QSD8650 has two flip-chip and one wire bonded die.

Figure 3 Plan-View X-ray Images of Qualcomm MSM8660 and QSD8650

Figure 4 is a side-view X-ray, and Figures 5 and 6 are optical cross section photographs, respectively, of the MSM8660 package. The MSM8660 assembly consists of a larger Qualcomm SoC die flip-chip bonded to a first printed wiring board (PWB 1) at the bottom of the package, and a second die wire bonded within a smaller ISM package, stacked over the bare SoC die and itself wire bonded to the main PWB (PWB 1). The embedded upper package contains a Samsung LP DDR2 SDRAM die wire bonded to the second PWB (PWB 2). Looking closely at the left image of Figure 6, we can see that the SDRAM was encapsulated before being flipped and laid on top of the SoC, before wire bonding the subassembly to the main substrate PWB1. There are also two passive elements bonded to the bottom PWB 1 and embedded within the package material.

Figure 4 Side View X-ray Image of MSM8660 Snapdragon Processor

Figure 5 Optical Cross-Sectional Image of MSM8660 Snapdragon Processor Package

Figure 6 Detailed Optical Cross-Sectional Images through the MSM8660

Figure 7 shows side-view X-ray images along the length and width of the QSD8650 package. The QSD8650 is also an fcPIP type package with two bare dies, an SoC and a DSP, flip-chip bonded to the PWB 1, and an SDRAM chip wire bonded to an upper PWB2 board, itself wire bonded to the PWB 1.

Figure 7 Side View X-ray Images of QSD8650 Snapdragon Processor

When comparing the packaging used for the 1.5 GHz MSM8660 and 1 GHz QSD8650, which represent two generations of processors manufactured with two generations of logic processors (45 nm and 65 nm, respectively), it is worthwhile noting that both processors are packaged with almost identical sized fcPIP type packages. The SoC processor die used for the two processors are almost identical in size. The MSM8660 processor package, however, has integrated a 512 Mbit DDR2 SDRAM chip with the SoC processor die, while the QSD8650 has incorporated a DSP chip in addition to a slower 512 Mbit DDR SDRAM chip, along with the processor SoC die.

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Analysis and reports on devices discussed in this blog

MSM8660 Snapdragon Dual Core CPU – Die Photos and Functional Analysis Reports

QSD8650 Microprocessor Die Photos

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Day 3 at the DAC featured an interesting panel called, “3D: Devils, Details, and Debate”.  A lot of people are expecting 3D chips to be the next big thing, but there are still a number of issues to conquer.

Matt Nowak of Qualcomm is concerned about the business model. The supply chain will be very complex, and the final devices will be very expensive. Who will stock inventory, who will be responsible for what parts of the reliability? Standards are needed such that all the members of the supply chain know what they are getting and delivering.

Raj Jammy of Sematech had other concerns. For 3D chips the wafers need to be thinned to an extreme, and handling of these wafers is currently an issue. He’s also worried about thermal hot spots. What if 2 stacked chips happen to have hot spots at the same spot. Overheating could easily push the chips too far and violate timing specs, if not worse. Who will be responsible for spec’ing hot spots on bare die? He’s also worried about stress. Through silicon vias (TSVs) used for 3D chips put huge stress on the die. However current advanced process digital transistors have about 40% of their performance due to stress engineering. What will happen when these stresses collide?  What design/layout accommodations have to be made to allow for it?

Indavong Vongsarady of STMicroelectronics had an interesting perspective. He considered that 3D chips were a solved problem, since ST had been using this technology in camera modules for a couple of years now. Chipworks has in fact analyzed camera module 3D structures a couple times now, including process analysis of the ST TSVs. We agree with Indavong that this is a solved problem in camera modules. See our reports for details.

Die Corner and Die Marks of STMicroelectronics Image Sensor with TSVs

TSVs in Cross Section

Bill Chen of ASE put these thoughts together for us. He agreed that in camera modules this was a solved problem. For that application all the technical hurdles had been passed. He also believes that IBM will soon put 3D chips into their servers. This will be tougher due to the thermal issues of running high powered processors in a stacked die configuration. But he believes IBM has the technology required and will be doing this very soon. He also thinks Intel could build 3D chips any time they want, but they are waiting for a killer app.  So far that killer app has not appeared, but memory stacked with application processors could be that soon enough. If so, look for Intel to jump in.

Junusz Rajski of Mentor concentrated on the test problem. 3D chips have a lot more circuitry than 2D, but only have about the same number of I/Os. Once again getting visibility into all the transistors and gates is getting tougher. Also, we will need better wafer test quality. If we are stacking 3 die, then a 10% failure rate at wafer test turns into a 30% failure rate after package. Clearly test needs to be better, but there are more things to test now. How does one test the TSVs before the chips are stacked?

Clearly more 3D chips are coming. The camera modules we’ve analyzed so far have been very interesting, with a few surprises we didn’t expect. We’re looking forward to the next application to use 3D chips with great interest.

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Fig. 1 Cross-Section of Texas Instruments XAM3715

This is the first time we have seen copper pillar technology since Intel adopted it a few years ago, but the style is different.  Looking closer (Fig. 2, click to enlarge), we can see that the plugs are tapered with some solder flow down the side, and it appears that the copper traces had been pre-coated with the same tin-based solder (likely SnAgCu).

Fig. 2 Close-up of Copper Pillar Bumps

The substrate is four-layer with two built-up layers (1-2-1), and the trace pitch is ~40 µm; in this section the pillars contact alternate traces, since the bond pads are staggered (Fig.3, click to enlarge).

Fig. 3 Plan-view Image of Bond Pads

Amkor published two papers [1, 2] at last year’s IITC and ECTC which together seem to describe the process.  Copper pillar bumps with solder caps are formed on the wafer (Fig. 4, click to enlarge)[1, 2] and the wafers are thinned, in our case to ~90 µm, and then singulated.

Fig. 4 Amkor Copper Pillars

Non-conductive paste (NCP) is pre-dispensed on the substrate and the die is thermo-compression (TC) bonded onto the substrate (Fig. 5, click to enlarge)[2].

Fig.5 Amkor NCP + TC Process Flow and Result

One difference that we noticed in the Sitara chip was that the pillar bumps were oval, as seen in the footprints in Fig. 3.  Fig. 6 (click to enlarge) shows a section at right angles to Fig. 2, and we can see the elongated profile of the pillar and the bond pad above, with a via going to a copper metal line above that.  In Fig.2 we also see some leakage of the solder down the sides of the pillar, maybe a function of the TC process using an oval shape.

Fig. 6 SEM Cross-Section of Pillar Bump

It appears that TI and Amkor have been using these pillar bumps for a while, since our sample was dated December last year.  In the meantime, we have seen the OMAP3630 in Motorola’s new Droid X and Droid 2 phones, so they have assuredly hit high volume production.
References
[1] Lee, C., Interconnection with copper pillar bumps: Process and applications, IITC 2009, pp. 214-216.
[2] Lee, M. et al., Study of Interconnection Process for Fine Pitch Flip Chip, ECTC 2009, pp. 720-723.

Related Chipworks Reports
[1] Texas Instruments / UMC XAM3715CBC 45 nm Application Processor   Package Analysis Report (PKG-1006-801)
[2] Texas Instruments / UMC XAM3715CBC 45 nm Application Processor   Structural Analysis Report (SAR-1007-801)
[3] Texas Instruments / UMC XAM3715CBC 45 nm Application Processor   Functional Analysis Report (FAR-1006-804)
[4] Texas Instruments / UMC XAM3715CBC 45 nm Application Processor   Exploratory Report (EXR-1006-801)
[5] Texas instruments / UMC OMAP3630 Application Processor  Functional Analysis Report (FAR-1008-801)

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