Contributed by: St.J. Dixon-Warren
Cree is the market leader in silicon carbide (SiC) device technology. They sell both material and a variety of discrete devices including LEDs and Schottky diodes. Recently, they launched a silicon carbide power MOSFET device, the CMF20120D, targeted at solar inverters, high voltage DC/DC converters, and motor drives. According to the datasheet, the CMF20120D is rated for VDS up to 1200 V with RDS(ON) of 80 mOhms, and with ID(MAX) at 33 A. The device is packaged in a standard TO-247-3 package.
The material properties of SiCs bring certain benefits. Foremost, an SiC has a much larger bandgap than silicon, hence SiC devices can operate at higher temperatures without suffering from thermally induced intrinsic conduction effects. An SiC device also has a higher breakdown voltage, meaning that devices can support higher voltages for a given device geometry. In addition, an SiC chip has higher thermal conductivity and higher electron drift velocities, enabling higher power and higher speeds.
Since the CMF20120D is the first SiC MOSFET available easily on the open market, we felt that an analysis was warranted. In this brief article, we share some of the highlights of our investigation.
Figure 1 shows a high resolution photograph of the CMF20120D die following decapsulation in Chipworks’ lab. The active region of the die is 3.46 mm x 3.46 mm. There are four wire bonds connecting to the source metallization area, while a fifth wire bond is connected to the gate contact pad on the left side of the die. Some simple measurements show that the source metallization area corresponds to 61% of the die area, while the gate pad and gate interconnect tracks correspond to 11% of the die area. The balance of the area is comprised of the inactive region around the periphery of the die.
Figure 1. CMF20120D Die Photograph
A detailed view of the corner of the source metallization area is shown in Figure 2. Each dark rectangle corresponds to a source contact to the SiC substrate. The contacts are surrounded by the polysilicon gate that lies beneath the metal. Each gate cell is 10 µm x 17.4 µm wide, hence a simple calculation estimates there to be 58,000 gate cells on the die. Consequently, when the device is conducting the highest rated drain current of 33 A, then each cell would carry ~0.6 mA.
Figure 2. CMF20120D Source Metallization Corner and Gate Cell Area
Figure 3 shows a cross section through the edge of the CMF20120D SiC die. The cross section location is shown in Figure 1. The device is a vertical drift MOSFET, hence the source metal and gate array are located on the top side of the 370 µm thick die, while the drain is located at the bottom side. The operation of a discrete power MOSFET is described on Wikipedia. When the device is off, then the full 1200 V rated voltage will be blocked between the source and drain, however, when the device is on, the source to drain resistance will be 80 mOhms. The switching time, according to the datasheet, is on the order of 30 ns to 80 ns.
Figure 3. CMF20120D Die Cross Section
The top side of the die features the source metal and a poly silicon gate array. Figure 4 shows a cross section through a single cell in the gate array. The transistor is comprised of source contacts to N+ diffusions that lie within the P-body. The N- drift region is formed using a layer of SiC epi plus the full thickness of the die.
Figure 4. CMF20120D MOS Gate Cell Cross Section
A more detailed view of the edge of a MOS gate is shown in Figure 5. The active channel lies between the edge of the N+ diffusion and the N- drift region.
Figure 5. CMF20120D MOS Gate Cell Cross Section Detail
The CMF20120D is the first easily available SiC vertical MOSFET device. This analysis shows that Cree has adopted a very conventional design for this discrete device. The next step will be the development of a SiC power IC that incorporates both control circuitry and power transistors into a single chip.
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