Every once in a while we like to play ‘reporter’ and talk about the things we see at industry trade shows. We try and relate what we learn to what our typical reader expects – which is a commentary on what is inside technology from a reverse engineering perspective. Our own Randy Torrance is at the Design Automation Conference, talking about reverse engineering and has taken some time to walk the floor and attend the conference.
All the usual suspects are at the Design Automation Conference. Cadence, Synopsys and Mentor all have large booths and a solid presence. TSMC has a booth straddling both sides of a main isle. But the booth that surprised me the most was GlobalFoundries. I didn’t do any square foot measurements, but they are in the running for the biggest booth here. And it blocks one of the most popular isles. It seems every time I get lost I walk right into it. They also seem very busy in other aspects of this show. Clearly they’re putting on a big push this year.
For most of the day I thought I would check out the sessions and see what was up and coming in EDA. I wasn’t disappointed as there were lots of interesting papers covering the gamut of IC CAD. But, as usual, we are looking for trends. Are there any overriding subjects that everyone seems to be talking about? The first one to jump out on day 1 was high level design. It looks like the EDA industry is doing pretty well at supporting most of the implementation stages of IC design. All the way from RTL to tape-out is pretty well served, but the creation of the original design at a high level seems to still be an issue. I guess it’s not a surprise, as 10 years ago everyone was happy to design chips using either of the main RTL languages of Verilog or VHDL. That worked well for million gate designs. But as we approach billion gate designs higher level languages have become necessary. And the EDA industry is trying to keep up.
In this morning’s keynote address Lisa Su, Senior VP and General Manager of Networking and Multimedia for Freescale Semiconductor made it clear that high level design is a major concern. One of her main issues is hardware – software co-design. In today’s complex chips it takes more effort to design the software than the hardware. However, the software design can’t start until there is some hardware to design it to. So problems aren’t identified until it is almost too late to fix them given the narrow market windows and heavy competition. Mrs. Su’s point was that “it” (the software) needs to be done quicker.
In fact, the software can’t even wait for the final chip design at tape-out. Electronic System Level (ESL) design needs to be good enough that it can be used as a Virtual Platform (VP) for the software to be developed on as soon as the ESL is complete (before RTL is even done).
At a luncheon given by Mentor Graphics this theme was continued. A collection of industry executives agreed that ESL was absolutely required, but not quite ready to solve all the problems yet. Gadi Singer, VP SOC Enabling Group at Intel requires ESL not just to enable designing more complexity, but also to speed up simulations, accelerate the design cycle, and reduce the lines of code needed to be verified by 10X. But mainly he needed ESL to allow early hardware software co-design. This theme was echoed by John Goodenough, VP of Design Technology at ARM, Ken Hansen, CTO at Freescale, and Jean-Marc Chateau, Director of System Platforms and Tools at STM. Jean-Marc stated that about 80% of STM’s SOCs were now designed partly using ESL. But he needs the other 20% to follow suit. He also needed ESL to find a way to incorporate power management.
The top 3 priorities of circuit designers are now 1) functionality, 2) performance, and 3) power management according to Jean-Marc. ESL has a good handle on the first, is doing OK on the second, but is not yet in the game for power. We need to do a bit of self promotion here, but Chipworks services also try to help companies address similar problems by showing them early on in the high level design, what other leading designers have done in the same or related chips.
So high level design is the watchword of the day. I guess it shouldn’t really be a surprise. It’s the decisions you make early on in the design cycle that have the most impact at the end.







