Chipworks

Contributed by: St.J. Dixon-Warren, Rajesh Krishnamurthy, Tim White, and James Mihaychuk

The coupling of an electrical signal, while providing high voltage galvanic isolation between two parts of a circuit, has always been a technical challenge. The main solution, since at least the early 1960s, has been to use optical coupling. The electrical signal is converted to light using a light emitting diode (LED) or even a small incandescent lamp. The light crosses the gap that provides the electrical isolation, and then the signal is converted back to the electrical domain with a photodiode or a photoresistor. Typically, opto-isolators are unidirectional devices; however, it is possible to build a bidirectional device by using a pair of LEDs placed face-to-face.

An example of a unidirectional opto-isolator is the Renesas PS9402, which was recently analyzed by Chipworks. The PS9402 is an optically coupled isolator containing a GaAlAs LED on the isolated input side, and a photodiode, signal processing circuit, and power output transistor on one chip on the output side. It also includes an isolated fault output. The PS9402 provides 5000 V breakdown isolation between the input and output pins.

Figure 1 shows a cross section through the PS9402. A signal from the input pins is converted to the optical domain by LED1. The light propagates across a gel filled cavity and is absorbed by the photodiode integrated into the BCDMOS die. The high voltage isolation gap is between the upper and lower lead frames. The LED2 is used to couple the fault signal back across the high voltage gap.

Figure 1. Renesas PS9402 Package Cross-Section

Optical isolators are a well established technology; however, due to the nature of the devices, they tend to have high package integration costs, hence a number of vendors have recently developed so-called “digital isolators” which keep the signal entirely within the electrical domain. A variety of different methods are used by the various suppliers of this new technology. The suppliers include Analog Devices, Infineon, NVE Corporation, Silicon Labs, and Texas Instruments. Chipworks has completed a suite of reports on these technologies. Some highlights of these analyses will be summarized here.

Analog Devices iCoupler digital isolators use monolithic planar isolation transformer structures to couple a signal across the high voltage isolation. The Infineon devices are based on a similar transformer technology. Figure 2 shows an X-ray photograph of the Analog Devices ADUM1200 digital isolator. The package contains two die. The transmitter die features three transformer coils, seen in the X-ray, that couple the signal across a layer of polyimide dielectric material.

Figure 2. Analog Devices ADUM1200 Package X-Ray

A cross-sectional view of one of the transformer coil windings in the ADUM1200 is shown in Figure 3. The cross section shows the top and bottom transformer windings separated by the polyimide insulating layer. According to the device datasheet, this polyimide can support up to 2500 V RMS.

Figure 3. Analog Devices ADUM1200 Isolation Transformer Windings

Texas Instruments and Silicon Labs use capacitive coupling to bridge the high voltage gap, rather than inductive coupling. The Texas Instruments ISO7220A is a dual-channel digital isolator. This device has a logic input and output buffer separated by TI’s silicon dioxide (SiO₂) isolation barrier, providing galvanic isolation of up to 4000 V. Figure 5 shows a cross-sectional SEM picture of the edge of the pads. The bottom capacitor plate is formed with an N⁺ substrate diffusion, with the top and bottom plates being separated by the full dielectric stack on the die. The Silicon Labs technology, shown in Figure 6, is quite similar, except that the top plate was formed with metal 6 and the bottom plate with metal 1, in a six metal CMOS process.

Figure 4. Texas Instruments ISO7220A Isolation Capacitor Edge

Figure 5. Silicon Labs Si8422BD Isolation Capacitor Edge

NVE Corporation digital isolators are based on a novel technology called GMR, or giant magnetoresistance. The GMR effect is observed as a significant change in the electrical resistance, depending on whether the magnetization of an adjacent ferromagnetic layer is in a parallel or an anti-parallel alignment. The overall resistance is relatively low for parallel alignment and relatively high for anti-parallel alignment. Figure 7 is a schematic diagram illustrating the operation of the NVE digital isolators. The magnetic field from a winding coil induces a change in the resistance of the GMR layer, which is sensed using a Wheatstone bridge structure. The benzocyclobutene (BCB) provides the high voltage electrical isolation. The GMR film is comprised of a thin, less than 100 nm, stack of permalloy (FeNi), copper, and antiferromagnetic CrPtMn. These films are deposited in the presence of a magnetic field, as described in the NVE US patent 7,557,562 B2, 2009.

Figure 6. Illustration of GMR Isolator

The NVE IL715-3E is a four channel unidirectional high-speed digital isolator. It is a CMOS device manufactured with NVE’s patented IsoLoop® spintronic GMR technology. The device apparently will provide 2500 V RMS isolation. Figure 8 shows the planar magnetic winding coils found on the top surface of the IL715-3E. The magnetic field from this coil results in a change in the GMR film resistance in the underlying Wheatstone bridge, shown in Figure 9.

Figure 7. NVE IL715-3E GMR Isolator Winding Coil and Bond Pads

Figure 8. NVE IL715-3E GMR Sensor Wheatstone Bridge

This brief survey illustrates the broad variety of technologies that have been used to bridge a low voltage signal across a high voltage gap. As discussed, optical coupling has historically been the method of choice; however, this is now being replaced by electronic methods based on inductive capacitive or magnetic coupling.

Chipworks Report References

• Analog Devices ADUM1200WTRZ Digital Isolator Process Review
• Analog Devices ADUM2200SRWZ Digital Isolator Process Review
• Analog Devices AduM1100AR-RL7 Digital Isolator Digital Isolator Receiver Partial Circuit Analysis
• Infineon EICEDRIVER® 1ED020I12FA IGBT Driver with Paired ICs and Planar Coreless Transformers 0.8 μm CMOS Process Process Review
• NVE IL715-3E GMR Type Digital Isolator (30457 J Die Markings) 0.50 μm CMOS Process Process Analysis
• Renesas PS9402 IGBT Driver with Photocouplers and 0.5 μm BCDMOS Signal Processor Process Review
• Silicon Laboratories Si8422BD Low-Power, Dual-Channel Digital Isolator TEM Analysis of Isolator
• Silicon Laboratories Si8422BD Low Power Dual Digital Isolator Circuit Analysis
• Texas Instruments ISO7220A Capacitor Type Digital Isolator Process Review
• Texas Instruments ISO1050DUB Isolated CAN Transceiver Circuit Analysis of Logic I/O Buffer

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contributed by St.J. Dixon-Warren and Tim White

Part 2 of 2 – the first article covered the discrete power MOSFETs in the LIN Bus I/O on the Atmel ATA6843 motor controller.

Power electronics is an area of particular interest for Chipworks, since it is a technology where innovation continues to be found. Power technology is often based on clever use of older process technologies. A particular area of interest for Chipworks is smart power ICs that integrate power transistors with an integrated circuit. Typically, these devices feature lateral diffused MOS transistors (LDMOS), but recently, Chipworks completed a comprehensive analysis of the Toshiba TPD4135AK including detailed process, electrical, and circuit analyses. The TPD4135AK features integrated lateral insulated gate bipolar transistors (IGBT).

The TPD4135AK is one of the most sophisticated and highest voltage smart power ICs that we have analyzed recently. The TPD4135AK is described by Toshiba as a brushless DC motor driver that uses high voltage pulse width modulation (PWM) control. It is fabricated in a high voltage SOI process, and has a three-shunt resistor circuit for current sensing. It contains a level shift high-side driver, low-side driver, IGBT outputs, fast recovery diodes, and protective functions for over-current circuit and undervoltage protection circuits, and a thermal shutdown circuit. The TPD4135AK enables control of a brushless DC motor simply by connecting logic inputs from a microprocessing unit (MPU) or motor controller to the TPD4135AK. All the functionality is integrated into a single silicon die in a 26 pin dual in-line (DIP) package.

Figure 1 shows the block diagram for the TPD4135AK from the device datasheet. The device integrates six IGBT transistors. IGBTs cannot conduct in the reverse direction. In bridge circuits, where reverse current flow is expected, an additional diode (sometimes called a freewheeling diode) is placed in parallel with the IGBT to conduct current in the opposite direction. The process analysis to be discussed here is focused on the IGBT.

Figure 1: TPDK4135 Block Diagram (click to enlarge)

Figure 2 shows a photograph of the TPD4135AK die annotated with the die architecture, as determined from the Chipworks full die circuit analysis. The six banks of IGBT devices occupy ~70% of the die. They have their corresponding reverse current freewheeling diodes (FWD) arranged, in sets of three for each IGBT bank, along the top edge of the die. Each IGBT bank contains 18 individual lateral IGBT devices.

Figure 2: TPDK4135 Annotated Die Photo (click to enlarge)

IGBTs are more commonly built as discrete vertical devices, with the emitter and gate on the top side of the die and the collector at the back side. The TPD4135AK uses lateral IGBT devices, where the emitter, gate, and collector are all fabricated on the top surface of the device. The operation of lateral IGBTs has been nicely described by Jong Mun Park in his PhD dissertation.

Figure 3 shows a portion of the top level schematic, extracted by Chipworks, for the TPD4135AK (the full top level schematic is here). As mentioned, each of the six IGBTs has a corresponding freewheeling diode.  According to the datasheet, the V_BB pins would be connected to the high voltage power supply (up to 450 V), while I_S pins would be connected to ground. The three phases of the motor are connected to the U, V, and W output pins. The freewheeling diodes are used to shunt inductive currents that come back from the motor.

Figure 3: TPDK4135 Portion of Schematic (click to enlarge)

A plan-view photograph of the end of one of the TPD4135AK IGBT individual devices is shown in Figure 4. The device is comprised of a central collector (anode) strip surrounded by a planar spiral poly resistor. The poly spirals out from the collector region to form field rings and, after six turns, reaches the MOSFET gate poly region, which lies adjacent to the bipolar emitter (cathode). The insulated gate transistor source contact is interleaved with the bipolar emitter contact, and its drain drift region also forms the base of the bipolar transistor.

Figure 4: TPDK4135 IGBT Plan View (click to enlarge)

Figure 5 shows the general structure of the lateral IGBT. The device is formed on a silicon-on-insulator (SOI) substrate, with a central collector between the two outer emitter strips. The control MOSFET transistors lie just inside the emitter strips. The buried oxide (BOX) provides complete isolation of the device from the substrate.

Figure 5: TPDK4135 General Structure (click to enlarge)

Figure 6 shows a detail SEM cross section of the emitter region of the lateral IGBTs. A silicon stain was used to delineate the doped regions. The stain does not easily distinguish the dopant type, but is quite sensitive to the dopant level. The dopant type for the emitter region was determined by using scanning capacitance microscopy (SCM); see below.  The micrograph shows the emitter contact adjacent to the NMOS gate. The P⁺ emitter also forms the body of the NMOS switching transistor.

Figure 6: TPDK4135 Emitter Region (click to enlarge)

Scanning capacitance microscopy analysis is required to reveal the dopant types used to build the lateral IGBT. Figure 7 presents an SCM micrograph of the emitter region. The SCM is sensitive to the dopant type, with P-type material giving a positive response (purple) and N-type material giving a negative response (yellow). Heavily doped material and undoped materials give a null response (pink). The SCM shows the emitter region to be formed with a P-type implant into the N-base material. The MOS gate is also N-type. The N⁺ source diffusion for the MOS gate lies at the top of the emitter, and is continuous in this cross section (plan-view SCM, not shown, reveals interleaved P⁺ contacts to the emitter).

Figure 7: TPKG4135 IGBT Emitter Structure (click to enlarge)

The IGBT collector, by contrast, is formed with a shallow P⁺ implant into the N-type base/drift region. The TPD4135AK IGBT, therefore, has the typical PNP bipolar device structure, with the gate controlling the majority carrier (electron) current to the base. This current then induces the injection of a minority carrier (hole) current from the P⁺ collector.

The TPD4135AK represents an impressive level of technology integration. It is built using a two aluminum metal, 3.5 µm BiCMOS process. It enables control of up to 450 V for driving a motor with TTL logic levels from an MCU.

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Contributed by Randy Torrance

As our esteemed blogger-in-chief, Dick James, wrote in a previous blog, we’ve recently been having fun tearing down numerous graphics boards. As he described, one of the boards we took a look at was the Radeon HD5750. Dick took a look at how a Samsung GDDR5 memory could support data rates of 5Gbps. In this article I look at how the GPU maintains this blazing speed.

The AMD/ATI Radeon HD 5750 graphics card uses a GPU with package markings 215-0754009-00, commonly known as the RV840. This chip uses ATI’s Juniper architecture (a member of the TeraScale 2 architecture family). The RV840 has a core speed of 700 MHz, 720 unified processors, 36 texture units, 16 blending units, 1.04 billion transistors, and a GDDR5 memory speed of 1150 MHz across a 128 bit memory data path. These are some very impressive numbers.

At first you might wonder why use a 5 Gbps memory when the GPU memory speed is only 1150 MHz. Ah, welcome to GDDR5. Firstly, as per all DDR (double data rate) memory interfaces, data is transferred on both edges of the clock. Therefore, an 1150 MHz clock transfers data at 2300 Mbps. Secondly, GDDR5 actually uses two clocks: CK and WCK. CK is the main memory interface clock, and commands can be sent on the rising edge of this clock (hence at a rate of 1150M commands per second). Addresses can be sent on both edges of this clock (2300M address per second). However, data uses the WCK, which runs at twice the rate of CK. Hence on the RV840 WCK runs at 2300 MHz. Since data can be sent on both edges of this clock, this data is transferred at 4.6 Gbps. So maybe not 5 Gbps, but pretty dang close.

As Dick found on the SGRAM, this chip too is flip chip, hence no bond wires. The bumps are distributed over the entire die, as can be seen in the x-ray in Figure 1 (the die is the darker rectangle in the middle). The package photo in Figure 1 also shows the liberal use of decoupling capacitors.

Fig. 1 Package Photo and X-ray (right) of ATI Radeon RV840

Once we popped the chip off the substrate, we can immediately see other concessions to the high required speed. As seen in the die photo (Fig. 2, below), the entire top metal, other than the bumps, is power and ground. We delayered this chip and found the majority of the top few layers of metal are power and ground. This allows for a low resistance and inductance path for power to the high-speed I/Os.

Fig. 2 Photo of ATI RV840 Die

Of course, an advanced process helps increase speeds. We cross-sectioned and analyzed the construction of this chip, and found the design is implemented in a 40 nm TSMC standard CMOS process (Figure 3). The cross-section also shows a very thick metal 8 and metal 9 layer. This helps keep the supply resistance low, allowing for less ground bounce and higher speeds for the I/Os.

Fig. 3 Cross-Section of RV840 Die

Once we delayer down to the polysilicon level we can see the structure of the GDDR5 I/O on the RV840. As shown in Figure 4, a block of GDDR5 I/Os is a complex beast. Each I/O is a highly complex circuit. Additionally each group of I/Os includes a PLL and 2 DLLs.

Fig. 4 RV840 I/O Block

We went ahead and extracted all the circuitry from this I/O block. It’s clear that supporting 4.6 Gbps I/O is truly complex task, as we ended up with over 300 schematics extracted. The circuits clearly implement a very sophisticated interface. As an example, Figure 5 shows the final stage of the output buffer. As can be seen, this is programmable with up to 6 independently controlled pull-up and pull-down stages. This circuit can be used to control not only the drive strength, but also the slew rate. Timing signals drive each of the pull-up and pull-down MOS. They are turned on and off by circuits controlling slew rates and drive strengths. The driving transistors are laid out with extended drains and sources to allow them to withstand the higher I/O supply voltage. A pair of resistors is used as the final stage to achieve optimal output impedance matching.

Fig. 5 Output Buffer Schematic

Clearly designing a 4.6 Gbps interface requires innovation on a lot of different levels. We’ve analyzed many different high-speed PHYs recently, including USB 2.0, USB 3.0, SATA, SATA 3, PCIe, PCIe 2, RapidIO, DDR, DDR2, DDR3, mobile DDR, and GDDR5 from a variety of vendors. The schematics extracted have a lot of common themes, but also a lot of differences. An example of a common theme can be found in the PLL of this GDDR5. A unit delay cell from this design is shown in Figure 6. Here we see a very commonly used technique, a flywheel. Inverters MI2 and MI23 are used to implement the flywheel design, creating a very accurately synchronized differential output. The layout for this circuit also shows attention to detail. This particular delay cell is in a group of 4. Figure 7 shows an image of the chip in this area, with the devices used in this single delay cell annotated in white (cross-probing on our schematic viewing tool allows us to choose a schematic circuit and highlight all its components in the images). As can be seen, all devices in this cell are actually split in two, and placed interleaved with the other delay cells’ devices. This will of course result in an even more well-balanced differential output. Most the high-speed PHYs we’ve analyzed recently use these techniques.

Fig. 6 Delay cell Schematic

Fig. 7 Delay Cell layout (Polysilicon Layer)

Chipworks reports on this device can be found at AMD/ATI RV840 Juniper GPU – Circuit Analysis Report of GDDR5 I/O Drivers, Receivers, DLL, and PLL.

Chipworks reports on the other high-speed PHYs can also be found in the Report Store.

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Plan-View X-ray of Samsung 1 Gb DDR3 SDRAM

Plan-view X-ray of Samsung 1 Gb GDDR5 Part from ATI Radeon

This is confirmed in the die photograph: 

Die Photo of Samsung 1 Gb GDDR5 SGRAM

 Which compares with the die photo of the 1-Gb DDR3: 

The die layout is clearly optimized to reduce RC delays from the memory blocks to the outside world.  The next question for me is the nature of the flip-chip bonding; is it regular solder bumps or gold stud bumps?  A cross-section solves that problem – solder, on plated-up copper lands. 

Cross-sectional Images of Samsung GDDR5 Chip in Package

A quick x-ray spectroscopy analysis tells us that the solder is silver-tin lead-free, confirming the package marking. 
So the answer to our question is actually fairly obvious – lay out the die to reduce input/output line lengths, and thereby RC delays on the chip, and replace bond wires with bumps to minimize RC delays in the package.  A nice exposition of basic principles used to optimize performance. 
The next step would be to co-package the memory chips with the GPU to reduce lateral board delays, and we have seen that in products such as the Sony RSX chip in the PS3 gaming system.  And after that, lay out the GPU for through-silicon vias – but that will be another story.. 

Stay tuned to this blog-site to see what circuitry is required for a GDDR5 PHY! 

Related Chipworks reports:
Samsung K4B1G0846F-HCF8 1Gb DDR3 SDRAM
Samsung K4G10325FE-HC04 GDDR5 Graphics SDRAM

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Next Sunday the great and the good of the electron device world will be gathering in San Francisco for the 2010 IEEE International Electron Devices Meeting.  To quote the conference web front page, “IEDM has been the world’s main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices.” 

From my perspective at Chipworks, focused on chips that have made it to production, it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years.

In the last few days I’ve gone through the advance program, and here’s my pick of what I want to try and get to, in more or less chronological order.  As usual there are overlapping sessions with interesting papers in parallel slots, but we’ll take the decision as to which to attend on the conference floor.

On Sunday December 5th, we start with the short courses, “15nm  CMOS Technology” and “Reliability and Yield of Advanced Integrated Technologies”.  Kelin Kuhn of Intel has organised the former, and we have some impressive speakers – Thomas Skotnicki (ST – Trends and Scaling), Mukesh Khare (IBM – Device Challenges), Sam Sivakumar (Intel – Lithography), Yoshihiro Hayashi (Renesas – BEOL), and Clive Bittlestone (TI – Device/Circuit Interactions). 

Having started in the business on 10-micron geometries, 15-nm devices seem crazy to me, but on the Intel clock it’s only three years away!  I’m starting to tell folks to think about the end of silicon, at least as we know it, since my brain will not wrap around the idea of 11- and 8-nm gates, and 11-nm is only five years away (and 30 – 40 atoms across, depending on orientation!).  The guys in the R&D labs have been thinking about that for the last decade or so (as we’ve seen at IEDM), so this should be an interesting day to see what they’ve come up with and how we get there.

The other side of the technology coin is reliability at these advanced nodes, and IMEC’s Guido Groeseneken has set up the other short course, with a slightly more academic slate of instructors.  We have Ben Kaczer (IMEC – FEOL), Shinichi Ogawa (NIAIST – BEOL), Christian Russ (Infineon – ESD), Ashraf Alam (Purdue – Reliability-Aware Design), and Andrez Strojwas (PDF Solutions – Yield, Yield models, and DFM).  Another good day – although the courses make a long Sunday, from 9 a.m. to 5.30 p.m., it’s worth sticking around to the end.

Monday morning we have the plenary session; a couple of good ones here, kicking off with Kinam Kim of Samsung, discussing silicon’s future (will it get beyond 11 nm?) and Arunjai Mittal of Infineon will discuss potential energy savings through the use of semiconductors – energy efficiency is one of the major themes of the conference this year.  The third plenary is on bionanoscience in healthcare, a whole new area to me; the plenaries traditionally make the link between semiconductors and other fields of science.

After lunch we get to the conference proper.  Straight into session 2, we have a set of 3D integration papers, by TSMC (paper 2.1), on integration at 28 nm, TSV-induced stress on HKMG (high-k, metal-gate) devices by Panasonic/Qualcomm/Samsung/IMEC/Newcastle U (2.2), and IBM (tungsten TSVs – 2.4), and some more academic institutions.

Session 5 on memory technology is split between traditional floating gate flash papers by Samsung (5.1) and Intel/Micron (5.2), and charge-trapping MONOS/SONOS flash, with two papers by Macronix (5.5, 5.6).  Micron and Samsung are touting their 25 and 27-nm (respectively) NAND flash technologies; Micron has solved the interline capacitance (wordline/wordline and bitline/bitline) problem by using airgaps:

Micron 25-nm NAND Flash - X-Sections of Wordlines and Select Transistors (top) and Bitlines (bottom) Source: Micron/IEDM

To my knowledge this will be the first volume production of air-gap technology in any product, even though there have been announcements by IBM and others discussing its use in the metal-dielectric stack.  It’s kind of ironic that this is in the process front end!  Laura Peters has been previewing a number of IEDM papers at ElectroIQ, and more details of this one can be found here.  We’ll see how Samsung gets around the same problem…

There’s also a paper from NCSU (5.3) discussing TaN floating gates down to 1 nm thick; if it works it will be a step towards vertically shrinking the NAND flash stack, something that hasn’t happened in the conventional two-polySi gate structure.

Intel have a couple of papers (6.1, 6.7) indicating where they may go at the 15- and 11-nm generations; both detailing Quantum-Well Field Effect Transistors (QWFETs), the former InGaAs finFETs, and the latter strained germanium pFETs.

Come 6.30 there’s the reception, a chance to see folks we haven’t seen since the last year, or at least since Semicon West, the last tech-fest I was able to get to.  Bring ear-plugs – a thousand-plus engineers yakking at the same time make a lot of noise!

Tuesday morning there’s a session on high-k and channel engineering, with the IBM Alliance tuning pFET VTH with a Ge implant (11.4, Laura’s take here), and TSMC/Nanyang U discussing gate stack annealing in their gate-last process (11.6, Laura)

Session 12 features another group of memory papers; Hynix is giving an invited review paper (12.4), and is co-affiliate with Grandis on a spin-torque RAM (12.7); and IBM (12.5) and Samsung (12.6) have papers on the same topic.

Session 13 is a highlight session of invited papers on “Next Generation Power Devices and Technology”, covering the field from silicon and silicon carbide to gallium nitride devices.

In the field of image sensors, TSMC has an invited paper (14.1) on a 0.9 µm pixel BSI (backside illumination) image sensor and the scaling challenges involved.  TSMC fabs the sensors for Omnivision, which are now at the 1.4 µm BSI generation commercially, so maybe we’ll see this one in a couple of years.  Omnivision have now migrated to a 300-mm copper process for their 1.1-µm part, just being launched.  This is how we get 12 Mpixel cameras in a cell phone!

Cross-Section of Omnivision OV5642 1.4 µm-Pixel BSI Image Sensor

The IEDM conference lunch speaker is Jim Clifford of Qualcomm, on the evolution of their chipsets and the technology required – we have just seen their first 45-nm part, and they are leaders in multichip packages; maybe we’ll get a hint of their 28/32 nm and TSV plans.

Macronix has a third paper (19.2) in the afternoon memory session on tungsten oxide resistive memory; and in the power session Panasonic (20.5) describes a high-voltage (>1300V) AlGaN/GaN on silicon device, and TSMC talks high-performance LDMOS (20.8).  In general the afternoon has a preponderance of academic speakers, with other sessions on device/circuit interactions, advanced processes, thin film transistors, memory simulation, and graphene (sessions 17, 18, and 21 – 23).

At 5.15 we have the first of three sponsored events; Applied Materials is holding a technical symposium, “Is Moore’s Law Taking Us in a New Direction? The Future of Transistor Technology”, around the corner at the Wyndham Parc 55 hotel, with a slate of speakers from GLOBALFOUNDRIES, IBM, Qualcomm, ST and other companies.

And if that’s not enough, there are the conference panel sessions back at the Hilton at 8 p.m. – “Heterogeneous Device Integration as Enabler of Functional Diversification for More than Moore”, which promises to range from nanomaterials to 3D chip stacking; and “Power Crunch – Threat or Opportunity?”, discussing power optimization at the transistor, circuit, and system level. 

By the end of those (if I’ve lasted that long) I will surely be getting into information overload, so I hope I sleep well, ready for session 27 on Wednesday morning, which covers off the advanced HKMG CMOS papers.

TSMC are discussing 22-nm FinFET process (27.1), Intel (27.2) have a HKMG RFCMOS review,  Qualcomm (27.3) are talking 28-nm low-power SoC technology (gate-first or gate-last – we’ll see!), and IBM (27.5) are updating the 32-nm eDRAM work they presented last year.  The odd paper out (27.4) is a more theoretical study by Texas Instruments of the way 1/f noise is affected by layout features such as active/active spacing and dual stress liner boundaries.

Cross and Longitudinal (right) Sections of TSMC 22-nm FinFET (Source: TSMC/IEDM)

In the parallel sessions Renesas is detailing microwave annealing of NiPt silicide (26.1), STMicroelectronics et al.(29.1) and NXP-TSMC (29.2) have phase-change memory papers, and Hynix (29.7) is showing off a 3D NAND-flash memory cell. 

Lunchtime, ASM is holding their fourth annual seminar with their own speakers and Mike Chudzig from IBM, on ALD and epitaxy in CMOS. 

Afternoon session 33 (novel processes) kicks off with an invited talk by Ichiro Mori of SELETE (33.1) on their EUV results; I’m not sure the concept of EUV is novel any more, but it’ll be interesting to see how far things have come.

Renesas has a paper on embedded DRAM with MIM capacitors in porous low-k (33.3), continuing the technology we have seen from the former NEC in the Nintendo Wii – now in volume production in their 55-nm process.

Embedded DRAM Capacitor Stack in NEC-Fabbed Memory Die From Nintendo Wii

A little later there is a talk by the IBM consortium on 32 nm BEOL using copper with a copper/manganese seed layer (33.5), followed by TSMC (33.6) discussing chip/package interactions when extreme low-k dielectrics are used.

In parallel sessions, TSMC have another FinFET paper (34.1), and a breakdown study of low-k dielectrics (35.2).  Toshiba have an interesting failure analysis study (35.3) looking at anomalous phosphorus diffusion by scanning spreading resistance imaging, followed by U. Cal, IMEC, and Infineon (35.4) examining the effect of strain on ESD protection devices.  Laura P. adds detail at ElectroIQ here.

By Wednesday afternoon a lot of attendees will be heading for home, and I’m usually thankful when the last paper’s done, but that’s not the end this year!  The SOI Industry Consortium is holding a workshop on fully depleted SOI starting at 5 p.m., with some notable speakers from academe and industry.  It will be in the Hilton, preceded by a reception and followed by a buffet supper to aid the weary bones and brain cells.

So as always, no peace for the curious!  I will be trying to post a more detailed blog as the conference unfolds, but given all the interesting topics being covered, time may be at a premium.  I hope to see you there!

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