Chipworks

Contributed by Vincent Karam.

Kicking off the afternoon of day 1 was the Ivy Bridge paper (3.1); the processor contains 1.4 Billion Transistors in an area of 160 mm² (for their 4 core 2 graphic segment die). The IVB dies were shown in four configurations, 4+2 (4 cores 2 graphics), 2+2, 4+1 and 2+1.

Here were some of the chip’s major highlights:

Quad-core with Intel Hyper-threading Technology

Next Generation Intel HD Graphics with DirectX 11 support

Dual channel DDR3-1600 or DDR3L -1333 interface

Integrated PCIe

Support for 3 displays simultaneously

Up to 8 MB cache memory

Same Thermal Design Power as predecessor

Next up was Intel’s 32nm Atom SoC with integrated WiFi codenamed Rosepoint (paper 3.4). Intel says it’s the first 32nm SoC with a WiFi transceiver and two Atom cores on the same die. They were able to get the Atom cores and the WiFi transceiver to get along nicely by choosing Atom processor frequencies such that their harmonics didn’t land in the WiFi frequency band.

Intel announces Atom-based WiFi chip Source: Intel

This was an obvious example of the direction Intel would like to push RF, into a scalable technology that keeps up with Intel’s fabs, so think digital CMOS. For most RF designers, including myself, it’s hard to imagine, but it’s something all RF designers will have to come to grips with.  Over the past few years Intel has been converting traditionally analog blocks to fully digital circuits (LNA ISSCC’01, Synthesizer VLSI’10, T/R Switch ISSCC’11 to name a few). On Tuesday Intel will also be presenting an all digital PA and Phase modulator, so you can add those to the list.

Intel’s third Microprocessor project, code named Claremont, seems to have received more attention by the media for different reasons than intended. This was a 32nm processor that demonstrated NTV (Near Threshold Voltage) operation as a means to optimize computational speed and energy (3.6). Although Intel used a solar cell to power the chip, Intel says they do not have any intention of producing solar powered CPU’s (at least in the near future). Power consumption can be as low as 2 mW, and it can operate on as little as 280 mV up to the conventional 1.2 V.

Intel's Claremont processor using NTV technology Source: Intel

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Contributed by Mike Christie

At ISSCC 2012, Samsung presented (paper 12.1) in the Multimedia and Communication SOCs session, entitled “A 32 nm High-k Metal Gate Application Processor with Ghz Multi-Core CPU.”

In this presentation, Samsung discussed its next generation Exynos application processor – we just recently finished a functional analysis report on the Exynos 4210. Samsung have already announced the Exynos 4212 (dual-core Cortex A9) and Exynos 5250 (dual-core Cortex A15), both of which are 32 nm HKMG.  Presumably, this one will be another in the Exynos series.

The specs on this processor include: two or four ARM-V7A CPU cores, with a shared 1 MB cache memory, each with a full hardware vector floating-point unit and 64 bit ARM NEON single instruction multiple data (SIMD) engine; a GPU containing quad core pixel processors, a single geometry processor, and its own 128 KB of dedicated L2 cache memory; and a dual channel DRAM interface capable of up to 6.4 GB/s and supporting LPDDR2, DDR2, and DDR3 400 MHz.

Block Diagram of Samsung's 32 nm Application Processor (source: Samsung/ISSCC)

The specs themselves are not particularly surprising, but the techniques Samsung has used to increase performance and reduce power consumption stand out.

The first major innovation is the switch from a poly-Si/SiON process to the HKMG process.  Their tests indicate that this process greatly reduces the leakage current in comparison to the old process (100x in gate leakage and 10x in overall leakage) with a 40% improvement in performance.

There are four power domains on the die: CPU, GPU, memory I/F, and media Ips. Each of these is further divided into power subdomains. For example, in the CPU domain, each of the cores is its own power domain, and each half of the cache memory. This allows for various power schemes to be used, depending on the system requirements.

Samsung has introduced a number of methods of balancing power and performance on the die, so that only the hardware needed for an application is used. The first of these is called DVFS, or dynamic voltage frequency scaling. The DVFS unit adjusts the operating voltage and frequency of the active blocks to meet the performance requirements of an application. By doing this, they have improved the battery life (for AP and DRAM only) by 34% to 50%.

The second method of balancing performance and power consumption is by means of body biasing. By using a Forward Body Bias, performance can be increased by as much as 13.5%, and by means of a Reverse Body Bias, it is possible to instead reduce the leakage current on a transistor, thereby reduce the power consumption.

Finally, there is the addition of a thermal management unit (TMU) which monitors the temperature of the system through thermal sensors, and maintains a constant temperature by throttling the various blocks, as necessary, through the DVFS controller. When the temperature in a block is determined to be too high, the performance will be reduced in order to maintain the temperature below a threshold. This not only helps to prevent burnout of the device, but also helps to reduce power consumption by as much as 32%.

Thermal Management Unit in Samsung's Application Processor (source: Samsung/ISSCC)

Samsung did not want to comment on the die size or many details of the process, as it is soon to be released to the press, but they displayed them at the demo sessions, along with their previous 45 nm generation, to show the improvements in performance.

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