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Layout Analysis – Gate Count
An estimate of the gate count of each digital block on a die. This information helps you understand what blocks their competition has found more efficient ways of implementing.
These reports include the following detailed information:
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Package photographs
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Package x-ray
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Depot (bare die) die photo
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Die size measurements
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Identification and size of minimum NAND 2 cell
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SEM plan-view image of minimum NAND 2 cell layout at poly
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Average standard cell gate density and total number of gates estimated
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Annotated metal 1 or poly die photo showing the digital blocks
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Best effort identification of functionality of digital blocks
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Estimate of gate count for each digital block
Download a sample report (5 MB) »