Contributed by Ray Fontaine, Senior Technology Analyst
It’s late spring of an odd-numbered year, which means it’s time for a 30-year tradition in the digital imaging community, where all come together for the International Image Sensors Workshop (IISW). The workshop is an exclusive event, intentionally limited in size to maintain an interactive atmosphere where the community can efficiently share and discuss its latest achievements and work in progress. Given Chipworks’ role of providing competitive technical intelligence reports and services, I was selected (and honored) to present on the technical trends we’re seeing in the latest mobile camera chips.
CMOS Image Sensors Market Continues Steady Growth
To set some context for a technical trends discussion, it makes sense to walk in from a market perspective and in general the CMOS image sensors (CISs) market continues its steady growth, likely hitting US $10 billion in revenue within the next year or so. This number is despite the negative growth phase of charge-coupled devices (CCDs), which still have their niches in specialty applications. Most in attendance at the IISW are inventors, so it seemed like a good opportunity to discuss patent activity as a benchmark of sector maturity. I visit a lot of imaging companies and when I ask technologists what keeps them up at night the common reply is “we’re worried we won’t have jobs in five years”. I suppose this fear is a reflection of the high quality of existing camera systems and maybe a bit of uncertainty about what more can be done. Fear aside, the market and patenting trends both suggest there is plenty of life left in the sector. As we head into the 3D integration era, I predict packaging inventions will rise as a percentage of the whole. It’s also natural that as the imaging community gains access to lower power and higher density processing all the dreams of years past will come to fruition in the form of innovation at the systems and software level.
On the technology side of things, I’ve been tracking the following trends:
- optical stack optimization,
- isolation techniques for crosstalk suppression,
- on-chip phase detection arrays, and
- chip stacking.
For the time being pixel scaling has essentially plateaued at the 1 µm generation so all the mobile small-pixel leaders have been looking for other knobs to turn. A lot of development has been done to embed color filters into the tungsten aperture grid metal. Sony and ON Semiconductor (Aptina) currently hold the world record (based on Chipworks’ analysis) for getting down to a 1.5 µm thick optical stack, as measured from the back-illuminated (BSI) silicon (Si) surface to the surface of the microlens. There doesn’t seem to be much more to do here, but time will tell.
Stacking Image Sensor Chips Like Sony
Sony has about a two year lead in the domain of stacking image sensor chips, and there is an important story to be told here. When I first became an image sensors analyst in 2007, one of the main criticisms of CCDs was that due to the highly specialized process flows required for CCD imaging array fabrication they would never be able to be integrated with a standard logic flow to realize a system-on-chip (SoC) imager for mobile use. So, CMOS won out and technologists worked really hard to bring light pipe technology and advanced fab processes up to speed to make SoC imagers, and later BSI chips into production.
So where are we now?
Sony has led the way back to a multi-chip solution, this time through chip stacking–essentially putting two chips into one. Depending on which flavor of Sony stacked chip system used, the image signal processor (ISP) can be either a homegrown (Sony) 65 nm chip or a TSMC fab’d 40 nm chip. A very thin BSI CIS fab’d by Sony is stacked on top and optimized solely to provide the best active pixel array possible with no worries of integrating logic or memory arrays. Through silicon vias (TSVs) and wafer bonding technologies are the primary enablers here and the rest of the small pixel world is following suit. My summary presentation slide and message was: if you aren’t excited about chip stacking, you should become excited about chip stacking! On this topic, Sony won the Walter Kosonocky Award for the best paper in the previous two years for its 2013 IEEE International Solid-State Circuits Conference (ISSCC) paper on stacked CIS technology.
Rather than try to summarize all the great work presented at the conference, I’ll briefly discuss some of the highlights of technology closest to the high-volume consumer imaging sector.
Samsung is quite proud of its 28 MP advanced photo system type-C (APS-C) BSI sensor and showed us the details of the two-row simultaneous readout (2RSR) used to enable 120 fps high speed readout in full HD resolution.
Canon presented details of its phase difference detection autofocus (PDAF) system for full frame chips. The dual photosites per pixel give an effective 9.2 million available autofocus points.
In a similar vein, Sony presented its full PDAF array which employs diagonal pixels split into left and right sub-pixels by means of a “micro-split-lens”, or µSL technology. The term is slightly deceptive in that dual photosites per pixel share a common microlens (rather than a dual microlens). Sony’s system also employs pixels and a Bayer-patterned color filter array rotated by 45°, and like Canon’s system, since there is no metal masking used for phase pixels, the AF system chip performs well in low-light conditions. It’s worth noting the philosophy behind this development effort – with the slowing of the pixel scaling trend, Sony is focusing on adding diversity to its product lineup through function-oriented imaging chips.
OmniVision gave a nice update on its stacked chip technology for 1.1 µm and 1.0 µm generation pixels, featuring buried (embedded) color filters and tungsten-filled back deep trench isolation (B-DTI). As we’ve recently discovered Sony’s IMX278 uses back-DTI it’s interesting that the big three of Samsung, Sony, and Omnivision are now all using embedded color filters and back-DTI (albeit OmniVision has filled its trenches with W). The end game for all the small-pixel guys is per-pixel TSVs in a stacked chip configuration for global shutter mode readout. OmniVision announced its continued development in this area and has apparently demonstrated 1.1 µm generation global shutter chips internally.
Olympus presented its stacked chip CIS with 4 million bumps on a 7.6 µm pitch to realize global shutter functionality in a 3.8 µm pixel size, 16 MP chip.
Photon counting is the most upwardly reaching technology
This blog posting is less coverage than the workshop deserves, however it’s a busy technology sector so I’ll leave it here for now. IISW 2015 was my fourth workshop and in my six years of attending, if I had one observation on ‘momentum’ I would have to mention photon counting as being the most upwardly reaching imaging/sensing technology. STMicroelectronics are the heavyweights in the SPAD domain and continue to demonstrate impressive results in low-light imaging, among other applications. It has now been 10 years since Eric Fossum introduced his concept of a quanta image sensor (QIS) and since that time the advances in low-power, advanced technology generation processing seems to be pushing us ever closer to the next paradigm shift.
Download my paper for free
For those who missed the workshop, my paper is downloadable here while the presentation material will be provided to members of our ChipSelect Image Sensors subscription service. The other 98 papers and presentations are expected to be available on the IISW online technical library website within a few months’ time.