Contributed by Dick James --- Follow me on Twitter @ChipworksDick
In my conference preview blog last week I mentioned that session 3 on the Monday afternoon would be a hot session, with three finFET papers, by TSMC, Intel, and IBM. I was right – even though they were given in the Grand Ballroom, it was full.
Paper 3.1 from TSMC disclosed what looks like their 16FF+ 16-nm finFET technology, advanced from the 16FF reported last year – although they don’t actually call it that in the paper. A 15% speed boost and 30% power reduction is claimed, or 40% speed gain and 60% power saving compared to the 20-nm process.
Gossip in the industry has it that 16FF was not advanced enough for TSMC’s customers, so they did some transistor engineering and cranked up the performance; 16FF is not even mentioned on the website these days, and 16FF+ is now in risk production, with endorsements by Avago, Freescale, LG Electronics, MediaTek, Nvidia, Renesas and Xilinx.
The 48 nm fin pitch and 90 nm contacted gate pitch announced last year were maintained, as is the 1x metal pitch of 64 nm. This level uses “advanced patterning scheme” – presumably self-aligned double patterning (SADP), whereas the other 80/90 nm pitch metals are done with single patterning. The low-k dielectric stack has been optimized relative to the 16FF process to give almost 10% capacitance improvement, and they have also added a planar high-k MIM capacitor (>15 fF/um2) for on-chip noise reduction.
At the transistor level, we have a dual-gate oxide process, replacement metal gate (gate-last), dual epitaxial raised source/drains, and tungsten local interconnect – but NO PICTURES! Lots of plots, but no transistor images, as in last year’s 16FF paper, and we were out of luck in the live presentation as well.
So we still have no idea of what the TSMC finFETs will look like. I guess that’s good for me and Chipworks, since we’ll have to wait until they actually show up in the real world sometime next year.
Intel gave a late news paper (3.7) describing their 14-nm finFET (note – finFET, not trigate) process at 4.05 pm. Being late news, there were only 15 minutes for Sanjay Natarajan to describe what looks like a technology that is distinctly changed from the 22-nm process. AND there were images!
As announced back in August, fin pitch is reduced to 42 nm, contacted gate pitch to 70 nm, and 1x metal to 52 nm, and we confirmed these in our blog on the Broadwell chip that we pulled out of a Panasonic laptop. In addition to the fins, the gates and the minimum metal levels use SADP, making for complex front-end lithography.
The fins have been modified from the 22-nm process to have a more vertical profile, slimmed down to 8 nm wide, and Intel also claims a “novel sub-fin doping technique” using “solid-source doping to enable better optimization of punch-through stopper dopants”. Sanjay’s presentation revealed that the solid-source doping uses a doped glass; now it’s down to us to work out when and where it’s used for punch-through inhibition. Idsat is claimed to improve by 15% for NMOS and 41% for PMOS over 22nm, and Idlin by 30% for NMOS and 38% for PMOS.
Changes have also been made to the back end – low-k dielectrics are used in the first eight levels, and significantly we see the first use of air-gaps in the M4 and M6 levels (80 and 160-nm pitch). This is Intel’s SEM image from the paper:
And here’s a TEM image from our analysis:
We can see from the spacing of the gaps and the profile of the barrier layer over the copper that a patterned approach has been taken, as described in the IITC 2010 paper , using a mask step after the formation of the metal seal layer.
Intel likes to point out their history – this is the second generation finFET, fourth generation HKMG, and sixth generation strained silicon; will their 10-nm be the third, fifth, and seventh generations?
I’m now inclined to think so, since at an Applied Materials event in the evening, when asked about the delay in the 14 nm launch, Mark Bohr was heard to say “We won’t have similar problems at 10 nm”. Mark does not make such comments lightly, so to me that implies two things – the 10-nm process is pretty well locked down already, and it’s unlikely that there are huge structural changes from the 14-nm generation. Indeed, the aggressive shrink from 22 nm to 14 nm puts them well on the way to the predicted 10-nm feature sizes.
Immediately after Intel’s talk IBM had their 15 minutes of IEDM advanced CMOS fame, describing their 14-nm technology. This has their fourth generation embedded DRAM, but is the first-gen finFET, and the first-gen gate-last process (and I’ve lost count of the SOI generations).
IBM claims a “unique dual workfunction process applied to both NFETs and PFETs” and sub-20-nm gate lengths, which will be the smallest we’ve seen if we ever get a sample. Being IBM, the intended product will be over 600 mm2 and have 15 metal levels, presumably their Power9 server chip.
Fin pitch is the same as Intel at 42 nm, but contacted gate pitch is 80 nm, and 1x metal is 64 nm. Here the fins are completely isolated since they are on the buried oxide, so no punch-through implants are needed at the base of the fin as on a bulk silicon substrate.
We do have pictures – these are really fuzzy, but we can see the gate wrapped over the fin with slightly raised source/drains on either side, and some nice facets on the source/drain epi.
During the presentation there were (of course) no details of the work-function materials, but it was stated that two masks were used to make the dual work-function structure; so presumably two slightly different material sets for the different work-functions. Another tidbit was that the pass-gate transistors in the e-DRAM had a different Vt than the logic transistors, but not achieved by a workfunction change.
I’d missed it, but the IBM alliance gave a paper at the VLSI conference back in June , where they describe a 10-nm finFET process; this look likes the same process, backed off to 14 nm and with the e-DRAM added.
The e-DRAM introduces some challenges in connecting the trench capacitor plate to the fin of the pass gate. In the planar 22-nm version there is a polySi strap from the polySi in the trench to the SOI on the buried oxide; in the finFET design the polySi strap is still used, but it is formed as a plug on the trench fill connecting to the SOI layer before fin definition, and the plug is etched into a fin during the fin etch. The epi module has been tuned to minimise the strap resistance and therefore the effect on access time.
Cell size of the eDRAM is now 0.0174 μm2; and if the trench capacitors are coupled together without the select gates, they can provide on-chip decoupling capacitors with a value of 450 fF/um2.
In the back-end IBM has their fifteen layers of metal ranging from 1x – 40x, and the section shows that the 40x is seriously thick, to take the power needed to run a chip this size!
That made for an eventful afternoon, with a bit of a disappointment from TSMC; we’ll look forward to seeing both their finFET and the Power9 next year. Of course we have a suite of reports on the Intel Broadwell, for those who want a detailed analysis of the part!
 H.J. Yoo et al., “Demonstration of a reliable high-performance and yielding Air gap interconnect process”, IITC 2010, pp. 1-3
 K-I Seo et al., “A 10nm Platform Technology for Low Power and High Performance Application Featuring FINFET Devices with Multi Workfunction Gate Stack on Bulk and SOI”, VLSI Tech 14, pp. 12-13